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Output states of a CMOS gate

  1. May 5, 2014 #1
    Please help me with the question in the picture about pull-up and pull-down networks.

    attachment.php?attachmentid=69451&stc=1&d=1399337661.png
     

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  2. jcsd
  3. May 5, 2014 #2

    meBigGuy

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    If your networks are replaced with single FET's, then, in general, yes, for steady state 1 or 0 input values.

    Even then though, when the input is (slowly) transitioning between 0 and 1 you can get other states (Z or crowbarred), depending on the threshold voltages.
     
  4. May 6, 2014 #3
    Thank you. That was a bit confusing.
     
  5. May 6, 2014 #4

    analogdesign

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    Also, you always get a crowbarred state for a short time when a logic gate is transitioning between logical states. That is where the power dissipation of CMOS comes from. It is also the source of supply bounce.
     
  6. May 6, 2014 #5

    meBigGuy

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    The short "crowbar" state during logic transitions is referred to as "shoot-through" and is only one source of CMOS current consumption and supply bounce. Another is the charging and discharging of gate and net capacitances. The Shoot-through portion of CMOS current can be very small or very significant depending on threshold and supply voltages. To the extent that the supply and thresholds are such that both devices can be on at the same time, shoot-through will be significant. But the charging and discharging on gate and net capacitances is generally a major contributer.
     
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