Parasitic capacitance influence on lead voltage

In summary, the question is about determining the influence of parasitic capacitance on V and its effect on reading accuracy. The solution depends on how V' changes over time, with a straightforward calculation for a sine wave and a more complex approach for arbitrary changes. This involves analyzing the RC circuit and solving the differential equation of the system.
  • #1
Marcis Rancans
9
0
V' changes over time. How can I determine the influence from parasitic capacitance (~50 pF) on V?
R wire ~ 100 ohm. If I need to read data (V' can change rapidly) from this at 50hz, does it influence reading accuracy? How can I determine values from which I need to be careful when reading data (when τ=RC>0,02sec ?)

https://lh5.googleusercontent.com/YxtTJvFj8vYphq43bW3FTw0ygk7D0WOJPVmzetsrsRsbclgyXy9ErGz6jA=s300
 
Last edited by a moderator:
Physics news on Phys.org
  • #2
This will all depend on how V' is changing over time. Is it a sine wave? Then the solution will be relatively straightforward to calculate. If V' changes arbitrarily, it won't be nearly as easy :)
 
  • #3
rumborak said:
This will all depend on how V' is changing over time. Is it a sine wave? Then the solution will be relatively straightforward to calculate. If V' changes arbitrarily, it won't be nearly as easy :)
V' changes chaotically.
 
  • #4
The problem is, all the easy tools that exist for analyzing circuitry presume a steady state, or at least a "periodic steady state".
What you have there is a type of RC circuit, and the only way to deduce the output from an arbitrary input is by solving the differential equation of that system.
For more:

http://en.m.wikipedia.org/wiki/RC_circuit
 
  • Like
Likes Marcis Rancans

1. How does parasitic capacitance affect lead voltage?

Parasitic capacitance is a type of unwanted capacitance that exists between two conductors. In the context of lead voltage, it refers to the capacitance between a lead (conductor) and its surrounding environment. This capacitance can cause a decrease in the voltage measured at the lead, as it acts as a parallel path for current to flow.

2. What factors can contribute to parasitic capacitance?

Parasitic capacitance is influenced by various factors such as the distance between the lead and its surroundings, the surface area of the lead, and the dielectric constant of the materials surrounding the lead. Additionally, the frequency of the signal passing through the lead can also affect the level of parasitic capacitance.

3. How does parasitic capacitance affect circuit performance?

The presence of parasitic capacitance can cause unwanted effects on circuit performance. It can lead to a decrease in signal integrity, as the capacitance can act as a low-pass filter and distort the signal. It can also cause a decrease in the accuracy of voltage measurements and affect the overall stability of the circuit.

4. How can parasitic capacitance be minimized?

There are various techniques that can be used to minimize parasitic capacitance, such as reducing the distance between the lead and its surroundings, using smaller lead sizes, and choosing materials with lower dielectric constants. Shielding techniques and proper grounding can also help reduce the effects of parasitic capacitance.

5. Can parasitic capacitance be completely eliminated?

While it is not possible to completely eliminate parasitic capacitance, it can be minimized to a level where its effects on circuit performance are negligible. This can be achieved through proper design and layout techniques, as well as careful selection of materials and components.

Similar threads

Replies
1
Views
62
Replies
1
Views
2K
  • Electrical Engineering
Replies
17
Views
2K
Replies
3
Views
1K
Replies
7
Views
1K
Replies
7
Views
1K
Replies
7
Views
1K
  • Introductory Physics Homework Help
Replies
4
Views
1K
Replies
2
Views
1K
Replies
3
Views
841
Back
Top