Processor and Memory data alignment with base pointers?

AI Thread Summary
The discussion revolves around the challenge of separating data from padding in a long string of characters (752 total, consisting of 0-9 and a-f). The user is working with a CPU operating at 2800MHz and 1024MB of memory, emphasizing the importance of data alignment based on CPU architecture, specifically x86. The conversation highlights how processors access memory, with some reading multiple words at once while others read byte by byte, leading to concepts like big endian and little endian. It is noted that memory alignment can result in wasted space, as data is often aligned on even byte boundaries or multiples of 4 or 8 bytes to optimize processor performance. The user expresses gratitude for the clarification provided, indicating that the information was helpful in understanding the issue.
drgibbles
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Hello, working on a puzzle and I think this may be what I need to do to solve it. I have a long string of characters,752 total with the range 0-9 and a-f. I believe that the data needs to be aligned based off the processor and memory. The Cpu is at 2800MHz and the memory is 1024MB. Is there a simple way or direction someone may be able to point me in regarding separating the data from padding? I know this is a little vague but I'm in unknown waters here, any suggestions would be greatly appreciated! Thanks for your time!
 
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drgibbles said:
Hello, working on a puzzle and I think this may be what I need to do to solve it. I have a long string of characters,752 total with the range 0-9 and a-f. I believe that the data needs to be aligned based off the processor and memory. The Cpu is at 2800MHz and the memory is 1024MB. Is there a simple way or direction someone may be able to point me in regarding separating the data from padding? I know this is a little vague but I'm in unknown waters here, any suggestions would be greatly appreciated! Thanks for your time!
What does that even mean ?
 
Sorry, let me see if I can straighten that up a bit. The way that data is stored is being based off the Cpu architecture, x86, and that coupled with the memory addresses. Here is a link that explains it some, but I'm just having a hard time wrapping my head around this.
https://en.wikipedia.org/wiki/Data_structure_alignment
 
Its not too hard to understand when you realize that the CPU imposes a certain preference in how it accesses memory.

Some processors read several words at a time and discard some bytes depending on the instructions. Others may read a byte at a time and shift it into a register. This is where the notion of big endian (mainframes and powerpc used big endian) vs little endian comes from (intel uses little endian).

This might also imply that there's wasted space in memory as data is aligned on even byte boundaries or even 4 or 8 byte boundaries taking advantage of the processor preference for such boundaries.
 
Thank you so much! That was exactly what I needed!
 
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