Engineering Redraw Equivalent Circuit for 3-input OR gate

AI Thread Summary
To redraw a three-input OR gate using only 2-input NAND gates, De Morgan's laws can be applied to create equivalent circuits. A NOT gate can be constructed by connecting the inputs of a NAND gate together, allowing for the formation of a 2-input OR gate through NAND configurations. The challenge involves ensuring the circuit outputs HIGH when at least two of the three inputs are LOW, which requires combining the outputs of multiple AND gates. The discussion highlights the complexity of achieving this with only NAND gates and suggests that implementing a majority circuit may require a similar number of NAND gates as directly constructing the OR gate. Clarity in the problem statement is emphasized for effective assistance.
Deathfish
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How do you redraw a three-input OR gate circuit using only 2-input NAND gates?
 
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Using De Morgan's laws, you should be able to figure out how to make a 2-input OR gate using NAND gates. You can make a NOT gate by wiring the NAND inputs together.
 
DeMorgan's law says
\overline{A+B}= \overline A\cdot \overline B

or

A+B = \overline{\overline A\cdot \overline B}= NAND(\overline A,\overline B)

So start with A + (B + C)...
 
Deathfish said:
How do you redraw a three-input OR gate circuit using only 2-input NAND gates?

You know the rules, Deathfish. Show us your work!
 
i've worked on this, but i seem to be going back and forth combining all combinations ie. 3C2 with no luck... difficult to explain this here. I know the equivalent of 2-input OR gates... but i am required to draw up 3-input OR gate when i am given just 2-input NAND gates. The question is to output HIGH when at least 2 out of 3 inputs are LOW.
 
Deathfish said:
i've worked on this, but i seem to be going back and forth combining all combinations ie. 3C2 with no luck... difficult to explain this here. I know the equivalent of 2-input OR gates... but i am required to draw up 3-input OR gate when i am given just 2-input NAND gates. The question is to output HIGH when at least 2 out of 3 inputs are LOW.

A 3-input OR gate does not "output high when at least 2 out of 3 inputs are low"...
 
its part of the question... A AND B, B AND C, A AND C then combine them together..
 
Deathfish said:
its part of the question... A AND B, B AND C, A AND C then combine them together..

Part of what question? Your original post says nothing about AND gates.
 
figured the first part out just need to combine that using three-input OR gate..
 
  • #10
Just guessing, are you trying to implement a majority circuit where two or more of A,B, and C are true? If so, it probably will take as many NAND gates to implement the 3 input OR gate by itself as it would to do the whole problem with NANDs in the first place.
 
  • #11
Deathfish said:
figured the first part out just need to combine that using three-input OR gate..

Thanks for being so clear in your OP. In the future, use the Homework Help Template, which asks for the exact problem statement.

I'm out.
 

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