Seeking Help with Gain Calculation

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Raju, a first-year Electronics and Electrical Engineering student from India, seeks assistance with calculating the gain of a JFET amplifier circuit he found online. He identifies the circuit as a differential FET cascode configuration but struggles with its analysis, particularly regarding the use of a 2N4401 transistor and a 100G resistor, which he finds unusual. Forum members express concerns about the circuit's stability and the unconventional use of an LED for biasing, suggesting it may be for temperature compensation. They recommend using a SPICE simulation program to analyze the circuit further. Overall, the discussion highlights the challenges of understanding complex amplifier configurations and the importance of circuit stability.
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Hi,

My name is raju and I am from India. I am in my first year of Degree doing Electronics and Electrical Engineering. I am having a bit of problem with this circuit I am attaching the circuit diagram.

Can anyone please tell me what is the gain of the amplifier and how can I found it. Please i would really appreciate if anyone can help me out. I am about to have my exams and i am preparing but i just can't figure out this circuit please help me..
 

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Welcome to the PF, raju. I've moved your post from the EE forum to here in the Homework Help forums.

How would you go about analyzing this circuit? What can you tell us about the various parts of the circuit? Why in the world is an LED being used (at very low current BTW) for the input stage current bias setting?
 
And the overall amplifier circuit does not appear to be very stable -- has this circuit been built or analyzed?
 
Hi,
No I have not build this circuit. I was searching on the internet finding some examples regarding JFET amplifiers when i came across this. I think that it is a Differential Fet cascode configuration in which one of the transistor is working as a voltage buffer and the other as a current buffer. I know how to work out the differential amplifier gain for BJT and I think same can be aplied for JFETs but i dnt have that much idea about the FET cascode. I am sorry i dnt know why he used an 2N4401 and specially the 100G resistor I have never seen someone using a 100G resistor.
 
raju20 said:
Hi,
No I have not build this circuit. I was searching on the internet finding some examples regarding JFET amplifiers when i came across this. I think that it is a Differential Fet cascode configuration in which one of the transistor is working as a voltage buffer and the other as a current buffer. I know how to work out the differential amplifier gain for BJT and I think same can be aplied for JFETs but i dnt have that much idea about the FET cascode. I am sorry i dnt know why he used an 2N4401 and specially the 100G resistor I have never seen someone using a 100G resistor.

The 100G resistor is just in the schematic for simulation purposes, most likely. It certainly is not a physical component. I also don't like the under-biased LED being used in the BJT bias circuit -- that's really goofy, unless there is some magic reason for using it.

Do you have access to a SPICE program? You could try simulating the circuit, although like I said, it sure doen't look like it has a very stable feedback arrangement. I doubt that the output opamp will appreciate all the phase shift and delay from having the diffamp in its feedback path...
 
I know this is an old post but I think the LED as the bias is for temperature compensation. I have seen this in transistor current source applications, never used it myself but the led junction has the opposite TC as the Vbe junction. Well almost.

re: From WIKI

http://upload.wikimedia.org/wikipedia/en/e/e8/Const_cur_src_113.gif
 
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