Hi everyone, I've been doing semiconductors lately,and believe me,I'm going absolutely nuts over it! This is especially when it comes to transistors. I have worked pretty hard,and I need to clear up some details before I can be confident in this topic. I'll put forward two questions that have been driving me crazy... 1. In common collector configuration (CC)of NPN transistor,there is a battery (Vce) connecting the collector (C) and emitter (E) which makes the C positive and the E negative due to the polarity applied...and there is another battery (Vbe)connecting the base(B) and E...which forward biases the B-E junction (am I okay till now?) Now,this is exactly the same as the CE configuration..so the electrons must flow in the same way in this configuration (CC)as in the CE ,and the magnitude of the current must vary in the same way on varying Vec and Vbe as in CE...so where's the difference? Also,I have noticed that in all three possible configurations,the B-E junction is forward biased and the C-B junction is reverse biased....then what differentiates them? 2. When we say that the 'input voltage' is through the base and the 'out put voltage' is through the Collector in the CE.....and this results to voltage amplification...what exactly do we mean? (As I said,in all configurations,in all three possible configurations,the B-E junction is forward biased and the C-B junction is reverse biased,so what allows to get different output voltage amplifications and different output characteristics in the three configurations?) These are very basic questions,I know,but I really need to get them cleared!