Suggest one way of sizing the transistors of the logic

AI Thread Summary
To size the transistors of a logic circuit so that its worst-case tpHL matches that of an inverter with a minimum (W/L) ratio, one approach is to maintain a specific ratio between the widths of the transistors. The discussion highlights that the worst-case ratio calculated is 3, although the method for arriving at this number is unclear. Participants express confusion over how the ratio was determined without numerical values provided in the problem. Clarification on the theoretical basis for sizing transistors in relation to inverter performance is sought. Understanding the relationship between transistor sizing and propagation delay is essential for achieving the desired performance.
bubothedog
Messages
7
Reaction score
0

Homework Statement


Suggest one way of sizing the transistors of the logic circuit such that its worst case
tpHL equals the tpHL of an inverter with a sizing of (W/L)min.

Homework Equations


I think the only equation is the (W/L) itself.

The Attempt at a Solution


I have actually done the front part of the question and I got the worst case ratio to be 3. But I am not too sure about the theory part to suggest a way. Anyone help?
 
Physics news on Phys.org
anyone?
 
I probably can't help with the question, but I wonder how you got "3" without any numbers given in the problem statement.
 

Similar threads

Back
Top