Homework Help: Toggle Flip-Flop Counter

1. Mar 30, 2013

planauts

1. The problem statement, all variables and given/known data
http://puu.sh/2qUr7 [Broken]

2. Relevant equations

3. The attempt at a solution

http://puu.sh/2qUwc [Broken]

I know that Q0 goes toggles 1/0 every rising edge. And Q1 toggles 1/0 every rising edge of Q0. And Q2 toggles 1/0 every rising edge of Q1. But I don't understand how the sequence becomes 000, 001, 010, 111.

Thanks!

Last edited by a moderator: May 6, 2017
2. Mar 30, 2013

LCKurtz

I don't understand what is puzzling you. The sequence you show in your solution is correct. The next state after your 111 will be 000 and it starts over.

Last edited by a moderator: May 6, 2017
3. Mar 31, 2013

AugustCrawl

So what you have here is a series of chained D-type flip flops much like this diagram:

http://www.bing.com/images/search?q...98C1C201365578950E83283BBF96B&selectedIndex=0

On a timing event (either a rising edge or falling edge) the value of T propagates to Q.
Notice that the clock is common to all memory storage elements - this is an example of a SYNCHRONOUS system. There is one clock and only one clock.

Let us make the reasonable assumption that at t=0 the values of the outputs at Q0 Q1 Q2 are all 0.

So at t = 0 seconds
Q0 = 0 Q0 = 0 Q0 = 0

Now let us pretend that they are all rising edge triggered and let Clock = 1 at t = 1 seconds

As the flip-flops sense the change in level the allow what is at their input to pass through them to their output

Q0 = 1 Q1 = 0 Q2 = 0

on the next rising edge we have

Q0 = 0 Q1 = 1 Q2 = 0

then we will have

Q0 = 0 Q1 = 0 Q2 = 1

I dont really see how this is a counter - I would call this a shift register with no feedback.

Unless the input labelled 1 is supposedly ALWAYS high and not just high at t = 0

000
100
110
111

Oh, okay... and the Q2 Q1 Q0 are labelled in reverse... hence Q0 is the LEAST SIGNIFICANT BIT.

000
001
011
111

So to summarise this is an example of using chained synchronous D-type Flip Flops (which are level triggered) to propagate an always high input over three clock cycles which trigger the memory storage elements with an always high input to create a counter.

4. Mar 31, 2013

planauts

Thanks I understand (sort of). However, the solution says: 000, 001, 010, 111. You have 011 instead of 010?

5. Mar 31, 2013

lewando

These are "T" (toggle) flip-flops, not "D"-type. When the input is a 1, at the time of the clock event the output will toggle. If the input were a 0, the output would not toggle, but rather hold its last state. Book answer looks correct.

6. Mar 31, 2013

AugustCrawl

I had though that latches were asynchronous elements (edge triggered) and that by combining them in clever arrangements we are able to form both +ve edge triggered -ve edge triggered and level triggered flip flops. I guess this T type must be an example of the "level triggered" variety. Thank you for the correction lewando :)