I do want to share what my interviews look like (as a candidate) normally for RF engineering positions. I'm still considered entry-level approaching mid-level with a little over 2 years of experience. Most of the interviews I've had are 6-8 hours long and I'll be interviewed by 4-8 people usually each one will have 1 to 1 although I've had groups of 2-3 people. Maybe it'll help someone else.
I am almost always asked to graph the step response of a RC circuit. I've been asked a few times to do it for a LC circuit.
I am almost always asked op-amp questions. Sometimes I'll be asked for all the different configurations including active filters, integrators, and differentiators. They might also give me periodic square waves or a step as the input and ask for what the output looks like for these. At one of the big tech companies they did ask for time domain response at each node, and the interviewer tried "breaking" the op-amp with diodes in very unusual places; it was not a practical circuit, but they were checking for understanding. All the interviews I've been on using KCL and KVL was very well-received. Sometimes they will ask a question related to having the output voltage being bigger than the supplies (say for instance your maths tell you it's going to be 5V, but the op-amp has a 3V supply), and also strategies to resolve this problem. Usually "reducing the gain" or "increasing the supply" is an acceptable answer, but they might follow up with an additional approach to solving that problem.
They'll ask about S-parameters. I'll typically have to draw a 2-port system and describe what each S-parameter by drawing out the arrows and labeling. They might ask for a 3-port system. I might be asked to draw any S-parameter plots for a broad or narrow band system. Sometimes they will ask me to cascade S-parameters. I think they run into a lot of people who thinking multiplying is okay (it's not). This might lead to talking about Y and Z-parameters, and ABCD matrix, but that doesn't happen always.
At the very least I am almost always asked about noise figure and linearity, and sometimes what it looks like on instruments such as a spectrum analyzer (or how to measure it). This is a good spot to trick candidates into asking about measuring the third order intercept; also to compare third order intercept to P1dB. Big tech companies will usually ask about units of noise and how noise is measured for a PSD. They might ask where in the chain would you prefer the best or worst noise figure and linearity in a chain; this may or may not lead into architecture questions. If it does, then you might have design a transciever on the fly and perform a link-budget. They usually do not provide the values I have to make it up roughly from the systems I've seen. This part of the interview is tricky because you might be "right", but for the "wrong" field (aerospace/defense versus consumer electronics). They might also ask which device in the chain is usually the least linear; what each filter does and how to roughly define its bandwidth. Only one place has asked a lot of questions about modulation schemes.
I'm always asked about layout and its flow. Particularly the cross-section of microstrip, stripline, and sometimes (grounded) CPW. They'll usually ask something like "If the characteristic impedance is too low we'll say ##30 \Omega## then how to correct it. You can do anything." Then you'll respond by how you can change the geometry of those transmission lines ie. if the impedance is too low you correct it by thinning the lines or thickening the dielectric, or (for CPW) widening the slot; you can choose a material with a lower dielectric constant. Sometimes they'll ask for "typical" dielectric constants and loss tangents. I'll also be asked how to choose which transmission line I'll use in a design (what are the advantages and disadvantages of each one). I've been asked once to draw the fields. I've also been asked to show what a stack-up looks like usually a 4-6 layer one and how to choose that as well, which layers will be dedicated to signal, power, and ground. A few places have asked about the process of making that stack-up and DFM questions.
I'll be asked about which tools I use. Any layout or simulation tools. This part usually also gets scrutiny even though you've disclosed which tools you use on your resume. Say for instance if you do layout usually with "layout tool 1" and you're interviewing for a position that uses "layout tool 2", then even though one person on the team thought the layout concepts were good enough there are still always people who do not care; it'll be difficult to convince them that you can learn and translate your knowledge between tools. I recommend if you are interested in working for a company find out which tools they use and try to get your hands on it; at the very least the (legal) free versions say for instance if they find Altium desirable then the free counterpart is
CircuitMaker. I don't see this problem when talking about simulations, but I'm considered very proficient with many of them including the ones I've heard others call "the gold standard." For both layout and simulations you might be able to find workshops on the company's website.
Modern RF engineers still use Smith charts. I've never had an RF interview that does not use a Smith chart. This is usually a brief 5-10 minutes of the interview. I have no idea why many of my older coworkers will try dazzling me with it as if it were some mysterious object they got from an archaeology dig site in a seventh world country. The most typical questions are asking to create a matching network given a load; I also be asked questions about short and open stubs and compare them for when they are less than, equal to, and greater than ##\lambda/4##. I'm rarely asked about Q factor and resonance although I've been asked; I've also been asked what the typical impedance (orders of magnitude) at different terminals of transistor looks like.
I have layout experience and so they'll continue with layout asking about a few approaches, component placement, and they might draw out a few areas of a trace or plane and ask you a few questions about it ie. they'll draw a trace going over a gap. I've had components placed for differential pairs. Roughly where I'll want to put "noisy" parts, and components such as LDOs or PAs known to get hot.
When LDOs get brought up sometimes we steer into switched DC-DC converters. I've had derive a buck, boost, and buck-boost during the interview. One of the big tech companies also asked me to show switch implementation (instead of using an ideal switch in drawing to use diodes and transistors). When the transistors get brought up here they might ask for the drawing of the cross-section of a MOSFET; they'll also ask about parasitics and how it affects the converter, and whether I would choose a pmos or nmos in certain areas and why. Because we're talking about converters we might talk more about PI and how to choose passives such as bypass capacitors.
For these rest I've probably been asked once or twice... do bode plots and Nyquist contours. Also using data converters I might even be asked to draw something conceptual or a block diagram of something connected to a data converter. A bit on sampling theory and folding. Some problems on measuring very tiny resistors or components on a layout (what might be wrong if I'm measuring ##500\Omega## when I was expecting ##50m\Omega##. I'll be asked about protocols like SPI or I2C. Someone had me use the propagation constant of a distributed elements to give them ##C_{eff}## and ##L_{eff}##. I've been asked about NEXT and FEXT also how to minimize or eliminate that. I've been asked how to convert differential into single ended. I've been asked coding questions; usually C or python is good enough. I've noticed that a common programming question will be play with the ++ or -- in front of the variable inside of a loop to see how the answer changes (if at all), and also logical operators including bit-wise ones. One interview asked me to prepare a presentation on a past project and I had to present it. Another interview (it was for an application engineer role) asked me to teach the interviewer something I was very comfortable with, which was surprising, but fun :). I think these last two I would prepare something even if you don't bring the powerpoint for the past project they might ask about it and it's great to refresh on what the project was, what challenges there were, and how you overcame it or why you couldn't. Trying to come up with something to teach during the interview can be scary so I would have a go to topic.
I had a bad gpa. I am always asked about my gpa. Big tech companies usually ask for you transcript; if not during the interview, then prior to getting an offer letter or at the very least when you are onboarding (if you are).
Salary expectations are almost always asked. I've seen general advice online is usually to try and dodge that question. I've never been successful in dodging it. Definitely come in with a number in mind and if you want to try dodging it then go for it, but if you can't then at least you came prepared.
