Re: What's the difference between successive approximation A/D and regular A/D conver

Yes, that is what every A/D converter does.

The difference is in how the A/D converter works internally, which has an implication on the performance it can give.

A successive approximation ADC uses 1 comparator and counts towards the signal.
This means a long conversion time.
And it won't be able to follow a signal that makes "jumps" correctly.

A direct-conversion ADC uses a bank of comparators to instantaneously convert the signal.
This implies a short conversion time, and it can follow jumps.
But it will be more expensive.

Re: What's the difference between successive approximation A/D and regular A/D conver

in real world environment a dual slope integrator with integration period of one power line cycle offers some benefits wrt line frequency noise rejection. But it's painfully slow.

Re: What's the difference between successive approximation A/D and regular A/D conver

Well, I am supposed to explain the principle of how successive approximation works. And I need to demonstrate this explanation. I'm sorry it appears like a HW is intruding, but that's what sparked it all.

I am tempted to just quote ILS. Problem is, even if I do, I need to demonstrate this successive approximation explanation based on the following A/D converter

There are no comparators and no counters that I can see...

Re: What's the difference between successive approximation A/D and regular A/D conver

Ahhh those sneaky fellows . The key word is in your post #1, "" via a binary search ""

In "Previous Page" at that link they describe an ADC that uses a free running counter which starts at 0 and increments one LSB at a time until it reaches the value of input. For 8 bits it would take 256 counts to digitize a full scale analog input. 128 for a half scale input.
The cycle stops after however many tries it took , max being 2^(number of bits).

The successive approximation starts instead with MSB and words sorta fail me here. So let me do an example.
Assume the analog input is full scale , 256 for our 8 bit example.

Set MSB only, that's halfscale and comparator recognizes that's not a big enough number.
So set next MSB, still not big enough
Set next MSB, still not big enough
and so on
until you set LSB and comparator recognizes that as the proper result., all bits set .
So you arrived at answer with eight tries instead of 256.

That's a binary search - where you eliminate half your choices with each test.
Had the number been too large at any point you'd just not set that bit and go on until all eight bits were tested.

So the successive approximation is usually faster than simple up-counter and perhaps a kind word for it is not out of order.
Certainly it's more predictable. It'll always take 8 trial cycles whereas the simple up-counter takes however many cycles are required to reach input - not many for small numbers but lots for large ones.

Recognizing that 8 bits is not a lot of resolution and even 256 tries wouldn't be outlandish. But what about those eighteen bit ADC's ?

did i get it across? Sorry for my ineloquence. I was "Born to Plod."