CMOS Regions of Operation Problem

  • Thread starter Thread starter tsaitea
  • Start date Start date
  • Tags Tags
    Cmos
Click For Summary

Discussion Overview

The discussion revolves around determining the regions of operation for two MOSFETs, M1 and M2, in a given circuit configuration. Participants explore the conditions under which each transistor operates, focusing on parameters such as gate-source voltage (VGS), drain-source voltage (VDS), threshold voltage (VTH), and biasing conditions. The conversation includes both theoretical considerations and practical implications of the circuit behavior.

Discussion Character

  • Technical explanation
  • Debate/contested
  • Mathematical reasoning

Main Points Raised

  • One participant identifies M2 as being in the triode region due to the drain-source voltage being zero, while expressing uncertainty about M1's region of operation based on VDS and VGS conditions.
  • Another participant suggests that for the FET to be on, the gate voltage must exceed the threshold voltage (VTH) below the source, proposing a condition that Vbias must be greater than Vdd plus VTH.
  • Some participants clarify that M2 does not affect the output voltage unless certain breakdown voltages are exceeded, and they discuss the conditions for M2 to be in the triode region.
  • There is a correction regarding the type of FET for M1, with one participant initially stating it as a P-type, while another asserts it is an N-type, leading to a discussion about the implications of this classification on the biasing conditions.
  • Several participants express that without specific values for bias and AC inputs, the analysis remains unresolved and unsolvable.

Areas of Agreement / Disagreement

Participants exhibit disagreement regarding the conditions for M1 and M2's operation, particularly concerning the type of FET and the necessary biasing conditions. The discussion remains unresolved with multiple competing views on the correct interpretation of the circuit parameters.

Contextual Notes

Limitations include the lack of specific numerical values for bias and AC inputs, which are necessary for a complete analysis of the circuit behavior. Additionally, there are unresolved assumptions regarding the definitions of the regions of operation for the MOSFETs.

tsaitea
Messages
19
Reaction score
0
In the attached photo, I found M2 to be triode region b/c the drain and drain source voltage is 0 which will always be less than the output voltage.

However, I am have troubles finding M1's region of operation, VDS >= VGS - VTH.
Vout - Vbias >= Vdd - Vbias - VTH **Vbias = 0.8 V , VTH = 0.5 V.

Vout >= Vdd - VTH

Im at this point now b/c Vout may vary.
 

Attachments

  • 20130307_172920.jpg
    20130307_172920.jpg
    21 KB · Views: 440
Physics news on Phys.org
For the moment assume Vin(t) = 0.

For the Fet to be on the gate voltage must be more than Vth below the source. In other words Vbias > Vdd+Vth.
 
You have not stated your problem.

M2 has no effect whatsoever on the output voltage unless the gate breakdown voltages are exceeded.
 
CWatters said:
For the moment assume Vin(t) = 0.

For the Fet to be on the gate voltage must be more than Vth below the source. In other words Vbias > Vdd+Vth.

So assuming Vin = 0, for the FET to be on VGS > VTH.

Where VG = VDD and VS = Vbias therefore,

VDD - Vbias > VTH

Vbias < VDD-VTH

I don't quite see where you got Vbias > Vdd + Vth from :confused:
 
rude man said:
You have not stated your problem.

M2 has no effect whatsoever on the output voltage unless the gate breakdown voltages are exceeded.

Right so for M2 Vout > Vth ,

For triode,

VDS2 < VGS2 - Vth
0 < Vout - Vth and since Vout > Vth,
M2 will be in triode.
 
tsaitea said:
So assuming Vin = 0, for the FET to be on VGS > VTH.

Where VG = VDD and VS = Vbias therefore,

VDD - Vbias > VTH

Vbias < VDD-VTH

I don't quite see where you got Vbias > Vdd + Vth from :confused:

M1 is a P type FET. So if I remember correctly the gate (VDD) has to be below the drain/source for it to be ON. Therefore Vbias must be > Gate + Vth.

M2 appears to be configured as a capacitor.
 
CWatters said:
M1 is a P type FET.

I don't think so. It's an N type.

The more conventional symbol for an N type is an arrow pointing into the substrate, but the alternative symbol is the source pointing away from the device, with no subtrate indicated.
.
 
Darn it you are right. I should have looked more carefully.
 
CWatters said:
Darn it you are right. I should have looked more carefully.

Well, without actual values for the bias and ac inputs the whole business is unsolvable anyway ...
 

Similar threads

  • · Replies 3 ·
Replies
3
Views
4K
  • · Replies 1 ·
Replies
1
Views
2K
Replies
1
Views
2K
  • · Replies 1 ·
Replies
1
Views
3K
  • · Replies 9 ·
Replies
9
Views
3K
  • · Replies 2 ·
Replies
2
Views
14K
Replies
13
Views
3K
Replies
2
Views
5K
  • · Replies 1 ·
Replies
1
Views
5K
  • · Replies 8 ·
Replies
8
Views
5K