Disconnecting source from inductor

1. Jul 16, 2012

ptxiao

Hi,

I'm working through a power electronics book and I'm looking at a half-bridge transformer-isolated buck converter (attached page). I've run into something that I can't fully understand even though the author presents it as something obvious. At 0 < t < D*Ts, the Q1 FET is conducting, and the Q2 FET is off. In this case V_T = V_g - V_cb, where V_cb is the voltage across the capacitor C_b. I can work out using inductor volt-second balance that V_T = 0.5*Vg during this period, as the waveform (second from top) shows, but only if I can accept that when both Q1 and Q2 are off, V_T=0.

When both Q1 and Q2 are off, one terminal of the transformer is disconnected. How does this lead to the voltage V_T going to zero?

Thanks

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2. Jul 18, 2012

es1

This is the Erickson text right? The short answer is it is zero because with both FETs open v_s(t)=0 and |v_t(t)|=n*v_s(t), assuming the diodes are ideal.

(I can't believe it took me like 4 edits to get that ideal transformer + rectifier equation right... I am mostly sure it is right now. :)

It is not that obvious to figure out why v_s(t)=0 and to do it you'll need to solve a system of equations which includes a volt-second balance on L.

Use the technique in this app note when they solve for the conventional asymmetric half-bridge.

http://www.fairchildsemi.com/an/AN/AN-4153.pdf

Last edited: Jul 18, 2012
3. Jul 18, 2012

uart

It's effectively forced to zero via the secondary. When both Q1 and Q2 are off the primary current must be zero*. For an ideal transformer if the primary current is zero then the net secondary current must also be zero. For the split secondary winding however, we can achieve a net zero current if we have equal and opposite currents in each half of the secondary, hence the load current freewheels through both D3 and D4 in parallel. The requirement of zero net current means that the transformer effectively forces them to share. (Note that the D3 half of the current flows out of the "dot" while the D4 half of the current flows into the "dot, hence no net current)

So with both D3 and D4 forward biased we can do a simple KVL around the loop contain D3, D4 and the two secondaries, and determine that the total secondary voltage must be $V_{D3} - V_{D4}$, which of course is 0 - 0 for ideal diodes and close to zero for real ones. Hope that helps.

*This is assuming an ideal transformer of course. If you allow for magnetizing inductance then the situation is more complicated, with D1/D2 allowing conduction to continue after the switches are off.

Last edited: Jul 18, 2012
4. Jul 18, 2012

es1

If you include Lm it still works as described. Notice Fig 6.21 of the attachment includes i_m(t). It's true that di_m(t)/dt=0 when Q1 and Q2 are off, but i_m(t) itself can be nonzero during this time.

Incidentally this is also why D1 & D2 are necessary. You can see the final blurb on them in the paragraph right before 6.3.2 in the text or this Google book link.

5. Jul 18, 2012

es1

It looks like you have to actually click on section 6.3.1 in the table on contents in the link provided to see the text from the book. Not sure why the link itself didn't work.

6. Jul 18, 2012

uart

Sorry that link doesn't seem to be loading properly for me (or maybe loading slow), so I can't see the images. But not to worry, as I know exactly what you're talking about. :)

Yes you're right, it would still work (almost) as described. The difference would be that the free-wheeling current would not divide exactly evenly between D3 and D4, with the current difference accounting for the magnetizing current (referred to the secondary). I was just trying to avoid explaining this for a simple solution relevant to the OP.

I was in error however when I said that inclusion of magnetizing inductance would cause D1/D2 to conduct after the switches were turned off. It is of course the inclusion of transformer leakage inductance that would give this outcome.