Does Gate Oxide Breakdown Voltage Vary with Bias Polarity in NMOS Transistors?

[t2000_wong]

For a NMOS transistor, is there a difference in gate oxide breakdown voltage if we apply a positive bias on gate and a negative bias on gate? (assume S/D/bulk are ground)

 

[analogdesign]

According to the paper
Hokari, Y, "Stress voltage polarity dependence of thermally grown thin gate oxide wearout" IEEE Transactions on Electron Devices, vol. 35, no 8, August 1998

there is a difference. In fact time-dependent dielectric breakdown lifetimes is one order-of-magnitude longer for positive biases and you get tunneling quicker with negative stress.