How can tri-state logic gates be used for shared memory busses?

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Discussion Overview

The discussion revolves around the implementation and significance of high impedance outputs in logic gates, particularly in the context of tri-state logic gates and their application in shared memory buses. Participants explore the circuit-level details and implications of high-Z states in digital logic.

Discussion Character

  • Technical explanation
  • Conceptual clarification
  • Debate/contested

Main Points Raised

  • Some participants inquire about the implementation of high impedance outputs in logic gates, specifically when using BJTs for a Not gate.
  • Others question the necessity of high-Z outputs, suggesting curiosity about their circuit-level implementation.
  • One participant notes that most logic gate outputs are low impedance and suggests that the discussion may be about three-state buffers, which have high-Z states that do not affect binary logic.
  • A participant discusses the implications of high-Z outputs in terms of DC analysis and mentions that while high-Z outputs can reduce power requirements, they may also lead to reduced fan out due to loading from following gates.
  • Another participant emphasizes the importance of tri-state outputs for shared memory buses, explaining that microcontrollers enable outputs from different memory types at different times, forcing high-Z states when not in use.

Areas of Agreement / Disagreement

Participants express varying levels of understanding regarding high-Z outputs and their implementations. While there is some agreement on the role of tri-state logic in shared memory buses, the discussion remains unresolved regarding the specifics of high-Z output implementation and its desirability.

Contextual Notes

Limitations include potential misunderstandings about the types of logic gates being discussed, as well as the implications of high-Z outputs on circuit performance and design considerations.

Who May Find This Useful

Readers interested in digital logic design, circuit implementation, and applications of tri-state logic in memory systems may find this discussion relevant.

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How is high impedance output implemented in logic gates?
If transistors(BJTs) are used to implement a Not gate, what would be the ckt when the output is high Z?
 
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Why would you want a hi-z output?
 
Why not?
Just curious to know how it is implemented at the circuit level.
 
Not quite sure what your are asking. When it comes to impedance of logic gates, most outputs are low impedance. Maybe you are thinking of three state buffers.
Three-state, or 3-state, logic gates have three states of the output: high (H), low (L) and high-impedance (Z). The high-impedance state plays no role in the logic, which remains strictly binary.
http://en.wikipedia.org/wiki/Logic_gate"
 
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I suppose if it is logic rather than an amplifier it is DC analysis as you are only interested in the on or off state of an output transistor except maybe dynamic analysis starts to become more significant at higher switching speeds when such as device capacitance plays a part. DC wise a high value of the collector to supply resistor will give a high Z ouput but it is not a desirable thing to have as following gates will load a hi-z output more and redcuce the 'fan out'. Maybe it will reduce power requirements in gates??
 
dlgoff said:
Not quite sure what your are asking. When it comes to impedance of logic gates, most outputs are low impedance. Maybe you are thinking of three state buffers.

http://en.wikipedia.org/wiki/Logic_gate"

I'm pretty sure that's what he's asking about -- thanks for posting the link.

Tri-state digital outputs are important for shared memory busses, for example. A microcontroller enables the outputs of ROM and RAM and Flash memory chips at different times when it wants to read from them. When not enabled to drive the data bus, these memory chips Tri-state their data outputs; The outputs are forced to high-Z by turning off both the pullup and pulldown transistors at the outputs stages.
 
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