How Does Mark-Space Ratio Affect Boost Converter Performance?

AI Thread Summary
The discussion focuses on the performance of a boost converter circuit and the unexpected results related to the mark-space ratio. The participant observed that a shorter "on" time resulted in a higher output voltage, contrary to their expectations. They raised questions about the relationship between switch-off time and output voltage, the behavior of inductor and capacitor currents, and observed voltage spikes during switching. Responses highlighted the importance of correctly interpreting the timing parameters and suggested that diode drops could affect output calculations. The conversation emphasizes the complexity of analyzing boost converter behavior and the need for precise measurements and adjustments in circuit design.
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Homework Statement



I have recently learned about the boost SMPS and and have built a circuit to investigate the waveforms and levels for Vout, [L] and [C] for different mark space ratios.

the circuit consists of a 95uH inducotr, diode, 47uF cap, 70 Ohm load, a FET who's gate is controlled by a PWM and a 5V input

The PWM is 25 KHz and here are the results i got for four different mark space ratios.

Code:
Vin   Vout  time period us   time on us   time off us   Inductor current  Capacitor current
5     14              40                  12.8             27.2               4.5 A                   4.2A
5      9.25          40                  20               20                  6   A                    6A
5      6               40                  30.4            9.6                 3   A                     3A
5      4.4            40                  40               0                    2.5 ma               2.5 ma [/I][/I]

My understanding is that the longer the time on is the larger the Voltage but this is the opposite in my results as the smallest time on is 12.8 us and gives the largest output voltage,.

I have been given some equations to work out the output voltage , inductor size etc but none of the seem to tally up. the Five questions i would like to ask are.

1) do my results seem correct?

2) does a longer switch 'off' time create a larger output( as per my results but opposite to what i thought would happen)

3) why does the current start to rise to 6 A and then drops to 3A.

4) i had a scope probe connected to the junction where the diode inductor and drain of the FET meet. on the display the there is a square wave which matches the duty cycle however on the rising edge of the FET switching on there is a massive spike in the region of 20 V and then it rings and dam pends down. what causes this? i did read somewhere about resonance? my theory was because there is a large back emf when the FET switchs off?5) how to calculate efficiency


2. Homework Equations

Vout = (T/Toff).VS
duty cycle =(1- (VS/Vout))
Inductor current = load current . Vout/Vs

The Attempt at a Solution


i have used the results from the first duty cycle i used in the firsat row of the table and you can see that they do not tally up??

Vout = (T/Toff).VS 40us/ 27.2us *5 = 7.35V
duty cycle =(1- (VS/Vout)) 1-(5/14)= 0.64
Inductor current = load current . Vout/Vs Load current = 14V/70 = 0.2A , 14V/5V*0.2 = 0.56A

PS i do apologize about the formatting of the table but I am not sure how to get the data ion rows and columns
 
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It would be helpful if you could attach a schematic diagram of your circuit. Also, a sketch or photo of the current waveforms.
 
photo 2.JPG
photo 3.JPG
photo 1.JPG
schematic.png
Hi,

Photo 3 trace 1 is the waveform at the node of the inductor, diode and the FETS drain, trace 2 is the output voltage
Photo 1 trace 1 is the current through the inductor measured with a "Pico technology" current probe.
Photo 2 is the rining on the rising edge of the pwm
 
Those all look as expected. It's often debatable whether ringing that's visible is actually there when you don't have the CRO leads attached, or whether this is introduced by the leads themselves introducing L and C on an aerial. For example, you could try a 220k resistor from gate to ground, this will probably clean up the appearance of the PWM waveform; capacitance from drain to gate or wiring capacitance may be feeding this back from the drain. You could try a 0.01uF in parallel with the electrolytic.

As a test, just resting your finger on some of these points may clean up the waveform, where the ringing is coming from a high impedance.

Energy in an inductor is ½LI² and this gets dumped into the reservoir capacitor when the FET turns off.

What is ߡV between the two DC levels in the yellow waveform? Is that big spike higher every second cycle?

You can see the inductor current is characterised by two linear regions. If you measure those slopes you should be able to compare them with what they should theoretically be. Remember, for an inductor v=L.di/dt

I'd say you're using a slow power rectifier diode there.
 
when i get back to univeristy next monday i will try adding the resistor and capaciotr to the breadboard and see what difference it makes.

what is still confusing me is the formula to calculate the output voltage.

The theory states Vout = (T/Toff).VS for the results in the table/ the pictures i get Vout = 40us/ 27.2us *5 = 7.35V . Which is not correct as the output can be seen to be roughly 14V in the third picture.

The spikes occur every cycle and are roughly the same hight give or take quarter of a division. it was hard to adjust the trigger to keep the trace still so the pictures were taken with the display stoped.

one last question is why does the current rise, peak at 6 amps then reduce?
 
tuttyfruitty said:
one last question is why does the current rise, peak at 6 amps then reduce?
I'd like it confirmed that the inductor current maintains that general waveshape over the whole range, before I think about that.
 
Yes your correct, the waveform is the same shape but the peak to peak value changes with change of duty cycle
 
I think there is a significant change in the inductor current waveform, but you are just not noticing it. Besides noting the peak-to-peak height of the waveform, can you take note of where the zero baseline is in the inductor current waveform for low output volts, midrange, and near-maximum.

Your table records values for capacitor current. How did you measure capacitor current, and what does the recorded value describe? Did you record the waveform?
 
tuttyfruitty said:

Homework Statement



I have recently learned about the boost SMPS and and have built a circuit to investigate the waveforms and levels for Vout, [L] and [C] for different mark space ratios.

the circuit consists of a 95uH inducotr, diode, 47uF cap, 70 Ohm load, a FET who's gate is controlled by a PWM and a 5V input

The PWM is 25 KHz and here are the results i got for four different mark space ratios.

Code:
Vin   Vout  time period us   time on us   time off us   Inductor current  Capacitor current
5     14              40                  12.8             27.2               4.5 A                   4.2A
5      9.25          40                  20               20                  6   A                    6A
5      6               40                  30.4            9.6                 3   A                     3A
5      4.4            40                  40               0                    2.5 ma               2.5 ma [/I][/I]

My understanding is that the longer the time on is the larger the Voltage but this is the opposite in my results as the smallest time on is 12.8 us and gives the largest output voltage,.

I have been given some equations to work out the output voltage , inductor size etc but none of the seem to tally up. the Five questions i would like to ask are.

1) do my results seem correct?

2) does a longer switch 'off' time create a larger output( as per my results but opposite to what i thought would happen)

3) why does the current start to rise to 6 A and then drops to 3A.

4) i had a scope probe connected to the junction where the diode inductor and drain of the FET meet. on the display the there is a square wave which matches the duty cycle however on the rising edge of the FET switching on there is a massive spike in the region of 20 V and then it rings and dam pends down. what causes this? i did read somewhere about resonance? my theory was because there is a large back emf when the FET switchs off?5) how to calculate efficiency


2. Homework Equations

Vout = (T/Toff).VS
duty cycle =(1- (VS/Vout))
Inductor current = load current . Vout/Vs

The Attempt at a Solution


i have used the results from the first duty cycle i used in the firsat row of the table and you can see that they do not tally up??

Vout = (T/Toff).VS 40us/ 27.2us *5 = 7.35V
duty cycle =(1- (VS/Vout)) 1-(5/14)= 0.64
Inductor current = load current . Vout/Vs Load current = 14V/70 = 0.2A , 14V/5V*0.2 = 0.56A

PS i do apologize about the formatting of the table but I am not sure how to get the data ion rows and columns
You're confusing Ton and Toff.
In your setup, Ton = 27.2 us. Look at photo 3 trace 1. The low part is for Ton.
So you should get Vout = 5V(40us)/13us = 15.4V. The diode drop accounts for most of the error.
 
  • #10
tuttyfruitty said:
when i get back to univeristy next monday i will try adding the resistor and capaciotr to the breadboard and see what difference it makes.
Any results to report?
 
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