Engineering How Is the Third State Achieved in a 3-State Circuit Design?

[mmmboh]

[PLAIN]http://img99.imageshack.us/img99/1046/fig9.jpg

This isn't actually homework so I'm not sure it should be posted here but I think it fits. In the notes the teacher wrote that in this figure to think about how the third state (disconnected) is achieved, and well I've thought about it but aren't sure. I have a quiz coming up and this is bothering me can someone help me please?

Thanks!

 

[chroot]

Hey mmmboh. Let's start by hearing what you think might be happening.

- Warren

 

[waht]

What's the truth table?

 

[chroot]

mmmboh, see, I figured you were really close to the right answer already. You've got it right. When the enable input is low, the two transistors are turned off by giving them zero gate voltage. (If you don't know what I mean, let me know.) When the transistors are turned off, their impedance is very high. That means very little current can flow through either of them, which effectively makes the output "disconnected." Usually, it's called a "high-impedance" state.

- Warren

 

[mmmboh]

So basically the MOSFETs are turned off by giving them zero gate voltage, and at this point the impedance is very high so their is little current which is like an open...
But yeah, I'm not EXACTLY sure what you mean by zero gate voltage, I'd be thankful for a bit of an explanation.

 

[chroot]

Sure, mmmboh. First, a definition. The "source" of a transistor is where its carriers come from. NMOS transistors, the ones on the bottom, conduct electrons, which come from the negative supply. So the source of the NMOS transistors is the ground rail at the bottom of the circuit. Everything's backwards for PMOS transistors, so their sources are the supply rail at the top of the circuit.

When I said "zero gate voltage," I implicitly meant "zero volts on the gate, relative to the source." The proper term is "gate to source" voltage, or Vgs.

When the gate is driven to the same voltage as the source -- like when the enable input is low -- the transistor has "zero gate voltage," and turns off. It takes about Vgs >= 0.6 or 0.7V to turn on common NMOS MOSFETs. (And Vgs <= 0.6 or 0.7V for PMOS.)

- Warren