1. Dec 14, 2014 #1

   desmond iking

   

   couldnt understand why the input is ( (XY)' (XY)' ) ' , IMO , it should be ((XY)' ) ' . because the 2nd logic gates receive (XY)' input from the first logic gates , and the second logic gates act as inverter for the first logic gates.

    

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   desmond iking, Dec 14, 2014
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3. Dec 14, 2014 #2

   jedishrfu

   

   Insights Author

   Staff: Mentor

   I think they did that because the (XY)' is the input to the second gate and both inputs are tied together then they said (XY)'(XY)' and the second gates output is then ( (XY)' (XY)' ) ' which can be reduced to ( (XY)' ) ' and the double negative to simply XY so it shows that two NAND gates can be used to construct an AND gate.

    

   jedishrfu, Dec 14, 2014
4. Dec 14, 2014 #3

   desmond iking

   

   Can I say the input is ((XY)' ) ' , which is also can be reduced to XY ?

    

   desmond iking, Dec 14, 2014
5. Dec 15, 2014 #4

   jedishrfu

   

   Insights Author

   Staff: Mentor

   Yes, I believe thats right.

    

   jedishrfu, Dec 15, 2014

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