Max clock frequency of flip-flop circuit

[thomas49th]

Homework Statement

Write down the setup and hold inequalities that relate to the second flipflop in each
circuit. You should measure all times from the rising edge of CLOCK. Identify which
of the circuits will not work reliably and determine the maximum clock frequency for
each of the others.

Homework Equations

Setup and hold times of the flipflops are 5 ns and 1 ns
respectively. Propagation delay of the flipflops may vary between 4 and 7 ns.
Propagation delay of the gates may vary between 2 and 6 ns. The signal C is a
symmetrical square wave.

The Attempt at a Solution

For A

We don't need to consider the 1st flipflop ever, because the second one "isolates" it. So we have a signal at H it needs to be there for 5ns as per the hold requirement. It will take 7 ns max for it to appear at I, so the clock peroid must be greater than

5+7 < T, which is correct => T < 83MHz

Now for B, again we shouldn't be concerned with the first flipflop, and hence our circuit is the same

therefore

5+7 < T => T < 83Mhz again

However, this is incorrect as now it should be 5+7 + 6 < T

I see that the 6 must come through the max delay from the delay gate on the first flipfop (causing the 1st flip-flop to be 6ns out with the clock for the second flipflop). Why does this matter? Apparently calculating 5+7 < T is incorrect. Why does the first flip flop affect the second making a 6 appear in 5+7 + 6 < T

Thanks
Thomas

 

[KataKoniK]

Hello Thomas,

Thank you for your question. The setup and hold times for a flipflop are important in ensuring reliable operation of the circuit. The setup time refers to the minimum amount of time that the input signal must be stable before the clock edge, while the hold time refers to the minimum amount of time that the input signal must remain stable after the clock edge. These requirements ensure that the flipflop has enough time to properly capture and store the input signal.

In the case of Circuit A, the first flipflop does not affect the second flipflop because it is not connected to the same clock. Therefore, the setup and hold requirements for the second flipflop are only affected by the propagation delay of the gates and the flipflop itself. This is why the calculation for the maximum clock frequency is simply 5+7 < T, as you have correctly identified.

In Circuit B, the first flipflop does affect the second flipflop because they share the same clock. This means that the first flipflop can introduce a delay of up to 6 ns on the input signal to the second flipflop. Therefore, the setup and hold requirements for the second flipflop must take this into account, resulting in the calculation of 5+7+6 < T. This is because the input signal must be stable for 5 ns before the clock edge, the first flipflop can introduce a delay of 6 ns, and then the second flipflop must have a hold time of 7 ns after the clock edge.

I hope this explanation helps to clarify why the first flipflop affects the second in Circuit B, and why the calculation for the maximum clock frequency is different for this circuit. It is important to consider all components and their delays when designing and analyzing circuits to ensure reliable operation.