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Max clock frequency of flip-flop circuit

  1. Nov 6, 2011 #1
    1. The problem statement, all variables and given/known data

    Write down the setup and hold inequalities that relate to the second flipflop in each
    circuit. You should measure all times from the rising edge of CLOCK. Identify which
    of the circuits will not work reliably and determine the maximum clock frequency for
    each of the others.

    FlipFlop_Timing_Same-3.jpg
    2. Relevant equations

    Setup and hold times of the flipflops are 5 ns and 1 ns
    respectively. Propagation delay of the flipflops may vary between 4 and 7 ns.
    Propagation delay of the gates may vary between 2 and 6 ns. The signal C is a
    symmetrical square wave.

    3. The attempt at a solution

    For A

    We don't need to consider the 1st flipflop ever, because the second one "isolates" it. So we have a signal at H it needs to be there for 5ns as per the hold requirement. It will take 7 ns max for it to appear at I, so the clock peroid must be greater than

    5+7 < T, which is correct => T < 83MHz

    Now for B, again we shouldn't be concerned with the first flipflop, and hence our circuit is the same

    therefore

    5+7 < T => T < 83Mhz again

    However, this is incorrect as now it should be 5+7 + 6 < T

    I see that the 6 must come through the max delay from the delay gate on the first flipfop (causing the 1st flip-flop to be 6ns out with the clock for the second flipflop). Why does this matter? Apparently calculating 5+7 < T is incorrect. Why does the first flip flop affect the second making a 6 appear in 5+7 + 6 < T

    Thanks
    Thomas
     
    Last edited: Nov 6, 2011
  2. jcsd
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