Power Electronics; full-bridge inverter

[sandy.bridge]

Homework Statement

I have three problems of the same type that I am wanting to tackle in the next 3 days, so I was hoping that I could get verification here that I am indeed getting the correct answers. I have my final exam coming up, and the section on these questions does not have any examples, and I cannot find any examples for the life of me!

Thanks in advance if you decide you can chime in and help me!

The issue I have is the determining the waveforms for the transistors. Since the load is inductive, the output current, and therefore the current through each leg when it is on will be lagging the output voltage. I am a little confused as to how a lagging current can possibly form such nice pulses at the output with a constant voltage source. Perhaps someone here can explain this to me?

 

[rude man]

Homework Statement

I have three problems of the same type that I am wanting to tackle in the next 3 days, so I was hoping that I could get verification here that I am indeed getting the correct answers. I have my final exam coming up, and the section on these questions does not have any examples, and I cannot find any examples for the life of me!

Thanks in advance if you decide you can chime in and help me!

The issue I have is the determining the waveforms for the transistors. Since the load is inductive, the output current, and therefore the current through each leg when it is on will be lagging the output voltage. I am a little confused as to how a lagging current can possibly form such nice pulses at the output with a constant voltage source. Perhaps someone here can explain this to me?

Put a square wave of voltage into an R-C lag circuit. The voltage is " ... nice pulses .." but what does the current waveform look like? NOT "nice pulses"! Same argument applies here.

 

[sandy.bridge]

Perfect! I was definitely over-thinking the situation. I think the main thing was that they are after the gate pulses, not the actual waveforms of current through the transistors, which would have been much more difficult to draw by hand and accurately.

 

[rude man]

Have you come up with the transistor base voltage switching diagram?

Part (a) asks for the base current waveforms. This is a difficult task. I wonder if they didn't mean base voltage waveforms.

The reason it's difficult is that here L/R is not << T. That means that some of the time appreciable load current will flow through the commutating diodes alone, so all base currents = 0 yet some of the transistors are commanded ON. This happens for example when the load voltage reverses polarity after the end of every half cycle. The difficulty lies in determining when the load current = 0.

For part (b) use Fourier series.
For part (a) if they really want base currents as functions of time, use PSPICE!

 

[sandy.bridge]

These are past final exam questions; simulation software is not an option. Any of the questions I have seen regarding these types of problems have been current signals applied to the gate. However, I do not see that as an issue. The signal applied to the gate is merely turning on the transistors. The current that passes from collector to emitter passes through the load; the load current lags the load voltage due to inductive nature. The parallel diodes will carry the load current whenever the output current's polarity is opposite to the polarity of the load voltage. The transistors should not be carrying any of the current during this time, this is the sole purpose of the diodes; to free-wheel the current when the transistors are off.

edit: I will post my drawing tomorrow when I have time to upload and hopefully you would be willing to give me feedback regarding it! I appreciate it a lot! It is these questions that are the most difficult, and I am hoping I can understand them by the final exam.

Also, do you know how to simulate this with PSPICE? I've been considering spending my break learning how to simulate circuits with MATLAB.

 

[rude man]

The signal applied to the gate is merely turning on the transistors.

The signal to the gate (I assume you mean the voltage applied to each base) is NOT necessarily to turn on the transistors UNLESS the base voltage is applied only when the load current is in the direction of the desired voltage. What means do you have to determine the direction of load current? Typically, in circuits like this, the answer is none. So the signals are applied to the transistor bases irrespective of the direction of load current, which of course works fine, the commutating diodes taking over to maintain the desired load voltage irrespective of load current direction. Which point it seems you understand well.

You should formulate your base voltage drive chart first, before you attempt to come up with the associated base currents. Those base currents will be zero when the load current opposes the applied load voltage, even though the applied voltages are at the "high" level.

 

[sandy.bridge]

Hmm. I managed to attain solutions from this professor for a very, very similar problem. The difference is that this problem has an on-time of 35 degrees as opposed to 30 degrees.

 

[rude man]

Hmm. I managed to attain solutions from this professor for a very, very similar problem. The difference is that this problem has an on-time of 35 degrees as opposed to 30 degrees.

OK, I see what they want. There are no actual currents shown, just "ON' vs "OFF" which is fine. I realized belatedly that all "ON" transistors are saturated anyway, so what I said about base current = (1/beta) * load current was nonsnse.

OK, why don't you proceed with your actual problem in the same way. And don't forget part (b)!

 

[sandy.bridge]

Alright. I did my work on loose-leaf and have uploaded it via pdf format! Thanks again for the help! Hopefully you can read all of that!

 

[rude man]

Your wave forms look right. I could not find any errors.

You also obviously know what you're doing in part (b). Therefore I won't check your math .

Good job!

 

[sandy.bridge]

I have two more interesting examples that are similar that I will be posting. Only thing I want more practice with is determining the gate signals, as the professor is bound to ask a similar problem on the final exam! I will post the problems with my solutions tomorrow, and if you have time, I would appreciate if you would look over it for me. Thank you again! Much appreciated.

 

[rude man]

I have two more interesting examples that are similar that I will be posting. Only thing I want more practice with is determining the gate signals, as the professor is bound to ask a similar problem on the final exam! I will post the problems with my solutions tomorrow, and if you have time, I would appreciate if you would look over it for me. Thank you again! Much appreciated.

Sure.

BTW there is more than one correct set of waveforms. For example, in the 1st half period you effected V = 0 by Q4 off and Q3 on. You could also have done Q1 off and Q2 on. Etc.

 

[sandy.bridge]

HI rude man,
I have one more waveform I was hoping you would check for me. It is similar to the problem before. I have attached both the question and what I believed to be the output waveform.

Thanks in advance!EDIT: I was also wondering if you saw my other thread where I was trying to determine the critical inductance for boost chopper to ensure it is continuous current. Thanks!

 

[rude man]

Your drawn waveform looks good. I checked thru 225 deg. only.

I don't see any computations of rms voltages or currents but I am confident you know what you're doing here.

I will look for your other thread, which sounds very interesting.