What is Clock Pulse in Digital Circuits?

AI Thread Summary
Clock pulses in digital circuits are essential for synchronizing the operation of flip-flops, which respond to transitions in these pulses. The clock pulse is not merely a power supply; it dictates when the flip-flops change states based on the input signals. Some chips may operate on the falling edge (high to low) of the clock pulse rather than the rising edge (low to high), depending on their design. The next state of a flip-flop, particularly in an SR flip-flop, is determined by its current state and the status of its inputs, with undefined states needing to be avoided. Initializing the output is crucial for circuits using feedback, as it prevents unpredictable behavior during the first operation.
vvkannan
Messages
21
Reaction score
0
wat is meant by the clock pulse given to the flip flops in digital circuits.
Is it just a supply that is given to the ic as long as it is held in on position.
How do some chips operate when the clock goes from high to low and not when pulses go from low to high?.
 
Engineering news on Phys.org
vvkannan said:
wat is meant by the clock pulse given to the flip flops in digital circuits.
Is it just a supply that is given to the ic as long as it is held in on position.
How do some chips operate when the clock goes from high to low and not when pulses go from low to high?.


This article should help you understand flip-flops. If you have questions about the article, you can post follow-up questions here.

http://en.wikipedia.org/wiki/Flip-flop_(electronics )

.
 
Last edited by a moderator:
what is the 'nest stat'.how do we obtain it in 'SR flip flop'
 
The... what?

- Warren
 
vvkannan said:
what is the 'nest stat'.how do we obtain it in 'SR flip flop'

If you mean the NEXT STATE, this only makes sense within context of a (finite) state machine (be it a single flip flop, or not). The next state of a state machine is the one that follows from the existing state (or, if you're going backwards, the state prior to the current one). Symbolically, this is Q(t+1) (the state of the machine at time, or step, t+1) as it relates to Q(t) (the state of the machine at time, or step, t).

In context of the SR flip flop, this depends on the current state of machine, and the status of the S(et) and R(eset) inputs:
http://en.wikipedia.org/wiki/Flip_flop_(electronics)#Set-Reset_flip-flops_.28SR_flip-flops.29

Not to be a grammar/spelling nazi, but there are spelling mistakes, and then there are spelling mistakes that completely impair the comprehension (by others) of what you are trying to say.
 
MATLABdude said:
Not to be a grammar/spelling nazi, but there are spelling mistakes, and then there are spelling mistakes that completely impair the comprehension (by others) of what you are trying to say.

Pretty helpful EE spelling/grammar nazi in this case :biggrin:
 
Terribly sorry abt that.
Its 'next state'
 
The LATCH CIRCUITS use enabling inputs and these latch circuits are called flip flops when the enabling inputs r connected to pulse detectors thereby making the circuit to respond only at the transtion of enabling inuts called as clock pulses. IS THIS RIGHT?

THEY say that the invalid state for the S-R flip-flop is maintained only for the short period of time that the pulse detector circuit allows the latch to be enabled. After that brief time period has elapsed, the outputs will latch into either the set or the reset state.I CANT UNDERSTAND THIS STATEMENT.please hellp me
 
vvkannan said:
The LATCH CIRCUITS use enabling inputs and these latch circuits are called flip flops when the enabling inputs r connected to pulse detectors thereby making the circuit to respond only at the transtion of enabling inuts called as clock pulses. IS THIS RIGHT?

If you mean that states only transition of "enabling" inputs (i.e. clock), then yes.

vvkannan said:
THEY say that the invalid state for the S-R flip-flop is maintained only for the short period of time that the pulse detector circuit allows the latch to be enabled. After that brief time period has elapsed, the outputs will latch into either the set or the reset state.I CANT UNDERSTAND THIS STATEMENT.please hellp me

S=R=1 is an undefined condition, which must be avoided (at least, when there's a transition at the clock input). These "undefined states" must be avoided as it results in an unknown output (may be either 1 or 0, with no guarantee that it is one or the other). The J-K flip flop covers this case (J=K=1), and uses it to Toggle the state of the flip flop (if output is a 1, it gets set to 0, and vice versa).
 
  • #10
thx for ur reply dude.so if j and k r made 1 and clock pulse is given then the the output depends upon the feedback from the previous outputs.
if the previous state is set r reset then the present state is reset r set respectively and this continues r otherwise toggles.is this right?
if so wat if the circuit is used for the first time? (i think this applies to all the feedback circuits)
 
  • #11
vvkannan said:
thx for ur reply dude.so if j and k r made 1 and clock pulse is given then the the output depends upon the feedback from the previous outputs.
if the previous state is set r reset then the present state is reset r set respectively and this continues r otherwise toggles.is this right?
if so wat if the circuit is used for the first time? (i think this applies to all the feedback circuits)

Sorry, I have a hard time understanding if 'r' means aRe, or oR. If it is 'are', then when dealing with the singular (as opposed to the plural), this should also be 'is' (the input is set high vs. the inputs are set low).

Grammar lesson aside, yes, J=K=1 toggles the output. You need to initialize the value first (set the output Q to either 0 or 1), however, or you toggle whatever the output is initially set to (something random).
 
Back
Top