Why is CMOS logic voltage standardized at 3.3V instead of 3V or 3.5V?

AI Thread Summary
CMOS logic voltage is standardized at 3.3V primarily for compatibility with 5V TTL logic while optimizing power consumption, speed, and die size. This voltage allows for a significant reduction in power dissipation, nearly 60%, compared to 5V systems. The choice of 3.3V serves as a target voltage, with actual supply ranges typically spanning from 3V to 3.6V. New generations of logic families are designed with goals such as backward compatibility and improved performance metrics. Overall, 3.3V strikes a balance between efficiency and functionality in modern integrated circuits.
likephysics
Messages
638
Reaction score
4
Why is the CMOS logic voltage exactly 3.3V, why not 3V or 3.5V?
 
Engineering news on Phys.org
"Logic Families" (http://en.wikipedia.org/wiki/Logic_family) are typically built for compatibility and involve "standards". A particular family generally employs identical silicon level transistors to perform a wide range of functions. Designing a die component requires considerable engineering, so it makes sense to reuse them.

A "new" generation is typically designed with specific goals in mind, including, but not limited, to backward compatibility, lower power consumption, faster response time, higher bandwidth and smaller die area. In most cases 3.3V logic can interface with 5V logic, but consumes less power, is faster and has a smaller die. 3.3V is certainly not the lowest voltage CMOS logic family, 2.5V and 1.7V logic are quite common in high density, high-speed ICs like RAM and Processors.

I hope that helps answer your OP.

Fish
 
Fish4Fun said:
"Logic Families" (http://en.wikipedia.org/wiki/Logic_family) are typically built for compatibility and involve "standards". A particular family generally employs identical silicon level transistors to perform a wide range of functions. Designing a die component requires considerable engineering, so it makes sense to reuse them.

A "new" generation is typically designed with specific goals in mind, including, but not limited, to backward compatibility, lower power consumption, faster response time, higher bandwidth and smaller die area. In most cases 3.3V logic can interface with 5V logic, but consumes less power, is faster and has a smaller die. 3.3V is certainly not the lowest voltage CMOS logic family, 2.5V and 1.7V logic are quite common in high density, high-speed ICs like RAM and Processors.

I hope that helps answer your OP.

Fish

Basically, if its not 3.3v then it wouldn't be compatible with 5v TTL?
 
It is a bit more complicated than that. You might have a look here:

http://www.interfacebus.com/voltage_threshold.html

for the actual voltage thresholds of various families of ICs.

From the article referenced above:

By lowering the power supply from 5V to 3.3V, switching power was reduced by almost 60 percent (power dissipation is proportional to the square of the supply voltage).

3.3V devices typically have supply ranges from 3V or less to 3.6V or more, so it is not so much that it is exactly 3.3V, but rather that 3.3V is more like the "target voltage".

Fish
 
Thread 'Weird near-field phenomenon I get in my EM simulation'
I recently made a basic simulation of wire antennas and I am not sure if the near field in my simulation is modeled correctly. One of the things that worry me is the fact that sometimes I see in my simulation "movements" in the near field that seems to be faster than the speed of wave propagation I defined (the speed of light in the simulation). Specifically I see "nodes" of low amplitude in the E field that are quickly "emitted" from the antenna and then slow down as they approach the far...
Hello dear reader, a brief introduction: Some 4 years ago someone started developing health related issues, apparently due to exposure to RF & ELF related frequencies and/or fields (Magnetic). This is currently becoming known as EHS. (Electromagnetic hypersensitivity is a claimed sensitivity to electromagnetic fields, to which adverse symptoms are attributed.) She experiences a deep burning sensation throughout her entire body, leaving her in pain and exhausted after a pulse has occurred...
Back
Top