thanks.
I think I somehow understand how double flopping benefits.
Yes, the short answer is Let's give a full cycle to metastable state to settle like many books say. But I believe this simple statement should be accompanied by a little more details(which is lacking in many digital design...
That's what most of the books say, but that's what I don't get either.
If you have a combinational logic driven by a single flop and this flop goes into metastability, that metastable signal also has a whole cycle to settle, doesn't it ?
Once one of the flops goes into metastable condition...
Suppose you design the digital circuit with D-flops and need to deal with asynchronous signals. Typical logic is receiving the async signal with a D flop followed by another D flop to deal with metastability. But how does double flopping benefit against the metastability ?
The first flop gets...
I know Veriog simulators are event-driven and what matters is the moment that event happens.
Suppose we have a code like,
module inv (in, out);
input in;
output out;
wire inv_s1;
reg out;
assign inv_s1 = ~in;
assign out = ~inv_s1;
endmodule
My question is does inv_s1...
You never know when you need it. If you went out somewhere for work and they only have old UNIX workstations, you don't have luxury to pick the editors and your only choice would be practically vi. Or what if your window manager fails to start ?
All you need to know is how to use esc, i, a, h...
OK, I found an old x86 book at home and just quickly read it.
Here is what I got(I corrected some part I wrote in #3 response as well).
Why are these useless ? Segment registers seem to point to the base address of segment current process is using. To me, it seems a simple form of TLB.
Yes...
I'm not an expert of x86, but in general, the address translation is performed in the similar ways on any processors, so here is my thought.
If you look at how the paging(or segmenting depending on how it is called) is performed, what an address translation table gives you is starting physical...
encoder, decoder and sequential circuit are very basic stuffs in logic design and any digital design books have this topic.
I have this book(older edition) and it's pretty good.
https://www.amazon.com/dp/0131863894/?tag=pfamazon01-20
Although I have 2 verilog books, neither is good and I...
Are you sending 0s or 1s from microcontroller to source of PMOSs when all of them gets turned on ?
if the gate is connected to gnd, sending 0 to PMOS's source will turn it off, but sending 1 keeps it turned on all the time. I suspect that your microcontrollers are sending 1s to all the PMOSs.
Yes. It's always good to process in 2^x data size.
If you design the 40bit processor, for example, you'll find the hardware will be complicated.
Suppose you design the cache memory for a 40bit processor.. What cache line size to pick ?
Due to the tag memory structure, the line size of the...
Nowadays, logic optimization is more than finding the theoretically best logical circuit. You need to consider the fanout, gate size, delay for each cells, power consumption, end-to-end overall delay...
But having a good algorithm is a must and if you have one, you have a great chance although...
Almost all the today's processors are based on byte address which means each address location is assigned every byte. To make the matter simple, it should be multiple of 8. if you want to have it 40bit, you can(IBM S/360 had 24bit address if I remember correctly), but logical step after 32 bit...