Constructing Complex CMOS Gates | Understanding NAND and NOR Logic

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The discussion focuses on constructing complex CMOS gates based on given logical expressions, specifically NAND and NOR configurations. It clarifies that a NAND gate consists of two PMOS transistors in parallel and two NMOS transistors in series, while a NOR gate has two PMOS transistors in series and two NMOS transistors in parallel. A participant seeks clarification on the rules for determining the arrangement of transistors based on expressions like (A+B). Ultimately, the participant concludes that they have figured out how to solve the problem independently. Understanding the arrangement of PMOS and NMOS transistors is crucial for constructing these gates effectively.
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Homework Statement


It given the expression
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. how to construct the complex CMOS gate by looking at the expression.


Homework Equations





The Attempt at a Solution



This solution is given as well.

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I don't understand how he construct it. I know NAND is fromed by two PMOS in parallel at top and two NMOS in series at bottom. NOR is formed by two PMOS in series at top and two NMOS in parallel at bottom.

Like, are there any rule that says, if I see (A+B), the CMOS should be in parallel or series...?

Thank you
 
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nevermind. I know how to solve it
 

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