3 Input Majority Logic Circuit

AI Thread Summary
A three-input majority logic circuit can be implemented using only 2-input NAND gates, with the goal of minimizing the number of gates used. The simplest known solution involves six NAND gates, but participants are exploring whether a more efficient design exists. The discussion reveals that the task is part of a pre-laboratory assignment, emphasizing practical implementation in a lab setting. Suggestions include considering the use of 2-input open collector NAND gates combined with resistor OR-ing to potentially simplify the circuit. Overall, the consensus leans towards six gates being the minimum required for this configuration.
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I want to implement a three input majority logic (when at least two of its inputs are 1, the output will be logic 1) by using only 2-input NAND gates. It is required to find the most simple one, with the lowest number of NAND gates, I could construct one with 6 NAND gates, but does anybody know a much simpler way for this? Or six gates is the simplest one? Any help is appreciated...
 
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Is this homework?
 
Actually, it is like a homework; it is a part of pre-laboratory which should be designed before coming to lab.. And it will be implemented on lab.
 
Using only 2 input nand gates I can't find a solution with less than 6 either.
 
Can you use 2-input open collector NAND gates (SN7401's) and resistor OR-ing?
 

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