Are Set and Reset Asynchronous in a D flip flop?

AI Thread Summary
In a D flip-flop, the set and reset functions can be either synchronous or asynchronous. Synchronous means that the reset is synchronized with the clock, activating only on a specific clock edge, while asynchronous allows the reset to occur independently of the clock state. The discussion highlights confusion about whether the set and reset should operate simultaneously or independently. Clarification is provided that asynchronous resets can override the clock, while synchronous resets depend on the clock signal. Understanding these distinctions is crucial for proper implementation in digital circuits.
mmmboh
Messages
401
Reaction score
0
I had a lab and I wrote they are asynchronous, so the clock input matters, but I am starting to doubt if I did it properly :confused:...what is the effect for both suppose to be simultaneously or independently?

Thanks.
 
Physics news on Phys.org
correct me if I am wrong, but I think synchronous = reset is synced with clock, meaning it will restart on a positive or negative clock edge(depending on the flipflop). Asynchronous means the reset will be forced, regardless of where the clock is at the given moment.
 
Thread 'Have I solved this structural engineering equation correctly?'

Thread 'Have I solved this structural engineering equation correctly?'

Hi all, I have a structural engineering book from 1979. I am trying to follow it as best as I can. I have come to a formula that calculates the rotations in radians at the rigid joint that requires an iterative procedure. This equation comes in the form of: $$ x_i = \frac {Q_ih_i + Q_{i+1}h_{i+1}}{4K} + \frac {C}{K}x_{i-1} + \frac {C}{K}x_{i+1} $$ Where: ## Q ## is the horizontal storey shear ## h ## is the storey height ## K = (6G_i + C_i + C_{i+1}) ## ## G = \frac {I_g}{h} ## ## C...
View full post »

Similar threads

Constructing a JK Flip-Flop: Troubleshooting Unexpected Outputs
Replies
20
Views
3K
Timing Diagrams for D Flip-Flops
Replies
7
Views
6K
Need help with a mod-6 counter using JK flip flops w/ control bit
Replies
1
Views
3K
D Latch and D type Flip Flop Question
Replies
1
Views
2K
D flip-flop, S-R master-slave flip-flop, falling edge of clock, NAND
Replies
1
Views
3K
T Flip-Flop Using A D Flip-Flop HDL?
Replies
1
Views
12K
Logic Design: Interpreting entering and leaving a room.
Replies
10
Views
4K
Engineering What is the Output of a D Flip-Flop Circuit?
Replies
1
Views
2K
Understanding Flip-Flop Type D: Negative Edge Triggering and Delay Neglect
Replies
22
Views
6K
Engineering Designing 3-Stage Async Counter & Logic Circuit in PSpice
Replies
5
Views
4K

Hot Threads

Recent Insights

Back
Top