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Full Adders and D-type flipflop help please

  1. Jan 7, 2013 #1
    Hi guys, just wandering if you could help me clear some things up regarding full adders and d-type flipflops?

    Firstly, regarding a d-type flip-flop, does the flipflop store the value which is received at 'd' and then send this to the output 'q' at the next available time (e.g. next rising clock edge or falling clock edge if negative triggered)?
    With a full adder, i understand that if two numbers A and B (1 and 1) are added, the binary output will be 10 and therefore carry (out) will = 1 and Sum(s) = 0, but what is the Cin (carry In) for? Is this from a previous full adder?

    Thanks :)
  2. jcsd
  3. Jan 7, 2013 #2
    Sorry to add but what are the feedback loops for on a D-type flip-flop? :)
  4. Jan 7, 2013 #3


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    Staff: Mentor

    The data bit at the D input is latched and clocked through to the output on the clock edge (whether rising or falling depends on which D FF topology you are using).

    Yes, the carry in would be from the previous bit in the adder. If it is bit 0 in the adder, the Cin would always be 0.

    Feedback us used to latch the data. Without feedback and latching, whenever the input data changed, the output would change. You need the feedback to have "memory". :smile:
  5. Jan 8, 2013 #4
    There are funny refinements with adders, especially circuitry called "carry lookahead" (Web search keywords), which shortens the carry chain by avoiding the carry signal to pass through every bit sequentially. Though, the "ripple carry" is perfectly possible and suffices for understanding.

    A D flip-flop memorizes always the value the D input had when its clock input told to sample D, and transmits this value to Q with no intentional delay - that is, a propagation delay is unavoidable but does not result from the clock.

    This opposes to a latch, which transmits every change in D when the clock has one level, and stops changing when the clock has the other level.

    Feedback is used at D flip-flops to make sequential machines. For instance, connecting D to the inverted Q lets the output change at every clock period, dividing the frequecy by 2. This wouldn't work with a latch. (Much) more refined feedback is used, for instance with 4 flip-flops to make a counter by 10 or 11 depending on one input, which is used at PLL. Or to create PN sequences, or to make the sequencer or a microprocessor... Then the feedback logic can be seriously complicated. In difficult cases this logi is created by a software and realized with suboptimum but regular building blocs like a programmable cell array.

    In CMOS technology only, a D flip-flop consists of two D latches with opposite clocks. This design is race-safe in CMOS, not in other technologies. TTL flip-flops had a completely different design. Race-safe design is very interesting but difficult.
  6. Jan 9, 2013 #5
    Could someone please explain what the it means by 'latched' and how this works? Im trying to understand how divide by 2 counters work and its the feedback bit thats confusing me :) Thanks
  7. Jan 9, 2013 #6


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    Staff: Mentor

    The simplest latch is a "Cross-Coupled NAND Latch" (or you can make it with NOR gates alternately). Have a look at the animation at this Wikipedia page (part way down on the right, showing the operation of the cross-coupled NOR latch:

    http://en.wikipedia.org/wiki/Flip-flop_(electronics [Broken])

    This structure is the building block for memories and FFs. You add extra stuff around it in order to implement different kinds of FFs with different features (like clear, set, etc.)

    For a simple ripple counter, just feed the output of on FF into the clock input of the next. The output of the first FF changes half as fast as its input clock, so the clock for FF2 is half as fast as the clock for FF1. That is how you get slower and slower square waves out of each stage of the ripple counter, and how it counts through the range of binary numbers at the FF outputs.


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