How to Solve a Timing Diagram with Multiple Logic Gates?

[Potatochip911]

Homework Statement

Draw the diagram for the following circuit given the following conditions:
1) X=Y=Z=1
2)X=Y=1, Z=0
3)X=Y=0, Z=1
4)X=1, Y=Z=0

Homework Equations

The Attempt at a Solution

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$W=XZ'+YZ$, $V=Y'Z+XY$

1) W = 0 + 1 = 1
V = 0 + 1 = 1

and now I'm not sure how to get the values for $Q$ and $Q'$ as for the nand gate:

a|b|out
0|0|1
0|1|1
1|0|1
1|1|0

so it appears as though having one of the inputs to the gate to be true doesn't provide any information without the other one input being known.

 

[Drakkith]

so it appears as though having one of the inputs to the gate to be true doesn't provide any information without the other one input being known.

If we assume that power has been removed for some time prior to providing the inputs, then the NAND gates should be outputting 0 to each other.

 

[Potatochip911]

If we assume that power has been removed for some time prior to providing the inputs, then the NAND gates should be outputting 0 to each other.

Hmm, now I'm confused because depending on whether or not I start at the top or bottom gate outputting 0 I will end up with either $Q=1$, $Q'=0$ or $Q=0$, $Q'=1$

 

[haruspex]

I would start by considering the four possible combinations of V and W. For each, consider how the four different states for Q and Q' transition from one to another. Some V, W combinations will produce a stable output for Q and Q', while others will produce cycles.