Solve Logic Circuit Troubleshooting Problem

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The discussion revolves around troubleshooting a digital circuit involving an 8561 fast comparator that fails to output a high signal despite receiving a negative pulse from a photomultiplier. The user has carefully followed assembly instructions and verified the photomultiplier's output with an oscilloscope. Suggestions include adjusting the input common mode range of the comparator by reducing bias voltage and checking the connection to the Latch Enable (LE) input, which may be floating high and causing the output to latch. The user plans to ground the LE input and investigate the bias resistor values to address potential oscillation issues. Overall, the focus is on resolving the input-output relationship in the circuit to achieve the desired functionality.
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I'm struggling with a digital circuit that seems to be defying my ability to troubleshoot and would appreciate any suggestions.

I received a pcb and parts list and followed the assembly instructions; I've done lots of kits before and I inspected my solder joints pretty carefully.

The gif attached shows the circuit, which feeds a pair of logic gates that control a counter. The IC is an 8561 fast comparator; a negative pulse at the jumper input is supposed to result in the output going high, which does not happen. The input device is a photomultiplier (pmt) which detects small pulses of light. I've looked at the pmt output on a scope and it is in fact a negative voltage pulse.

Initially, the input pins are both low. When I apply a light pulse to the pmt, the input goes high. The output of the comparator (according to my logic probe) does not change. What's going on between the input and the comparator that should make the negative pulse send the comparator high?

Thanks.
 

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It's a little hard to read the gif, but here are a couple of thoughts:

-- The input common mode range of that comparator only appears from the datasheet to go up to about half of the power supply voltage. It looks in your circuit like the inputs are being biased up pretty close to Vcc/2, so you could try reducing that bias down closer to just 1V or so to see if the comparator acts better.

-- Is there any chance that the connection to the Latch Enable input is not being made? If there is no pulldown attached, then the Latch Enable pin will float high, and the output of the comparator will be latched and not reflect any changes at the inputs. It looks like your kit is trying to use the LE input as a way to cut down on oscillations at the output, since they are not using explicit hysteresis feedback. If it were me, I'd lose the LE stuff, just ground the LE input, and add your own explicit hysteresis feedback as part of the bias circuit.

Hope that helps some. -Mike-
 
To reduce the bias, would you increase a resistor value?
There is some oscillation, visible as pulsing in my logic probe when the comparator's output (pin 7) is low. I will try grounding LE as you suggest.
Thanks,
Dan
 
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