Flip flop Definition and 38 Threads

In the RS flip flops using a NOR gate if we replace the NOR by an OR gate all the outputs will be indeterminate. Both outputs Q and Q' will every time yield 1. Can you explain how the inputs 0 and 0 will give 1 1 as output

Hello! I am confused in a question I found on youtube. I have uploaded the screen shots. He told that with respect to S and R we have to write the change from Q to Q+( next state). But I am not getting it. How he wrote Q+ states?Is he considering that when S=1 , we have to set the circuit i.e on...

Homework Statement Hello everyone. I tried practicing creating up down counters using the J/K FF. I've been using the Synchronized Clock with an up down counter and the simulation seems to be successful based on this circuit on the image However, in the actual circuit in a breadboard using a...

Hi, Can current flow both ways through a NOT gate, or is the diagram I saw, much like the picture I drew here, just drawn the wrong way around? Anyway, say it was correct, so what does this mean? Because the chip itself (the not gate chip Vcc = 5V and Gnd) takes 5V between it and the chip...

Hello, I am building a prototype of a balance indicator to prevent farm quadbike to roll on steep hills. I am using an arduino pro mini and 2 sets of assignable strips of 8 leds (https://www.adafruit.com/products/1426) and a gyro-accelerometer sensor. To power it, I am using the farm motor bike...

Tried using the template, had to put pictures because this concerns a diagram question! sorry guys! 1. Homework Statement Consider the circuit shown in the figure below which consists of a positive edge triggered flipflop with selective load capability (identified as MICK) and a level...

Homework Statement Hello, I am thinking about the operation of the D latches and Flip Flops. I know the operation of Latch : When clock is hi: -Q follows D in simple combinational behaviour - D/Q path is transperant ( what I think it means what is on D can be seen on Q) ? At...

I need help! I'm really close to figuring out this Control Relay circuit but I'm running out of time. Circuit Description: Plug in the circuit and the light turns on. Press the momentary button and the light goes off. Press the momentary button again, and the light turns back on...

Homework Statement I have to construct a circuit for my Physics class. The circuit must be tripped by a CDS Cell (Detects changes in light) and, once being 'tripped' it must play a continuous sound and make an LED flash on and off. This picture is of the circuit board we are allowed to...

I've lately been going through the Nand2Tetris course since I never had the chance to take anything like it in college, and in its chapter on sequential logic , it treats the D flip-flop as a fundamental component. I found that somewhat unsatisfying, so I went and started reading up on...

I was studying this from some info in found online and i couldn't understand something: "Although this circuit (J-K) is an improvement on the clocked SR flip-flop it still suffers from timing problems called "race" if the output Q changes state before the timing pulse of the clock input has...

Homework Statement What does flip flop with clock enable mean and what is the next state equation for D flip flop with clock enable?

NB: Got a bit wordy, highlighted question in red. Homework Statement Just a picture of what we're dealing with. I'm given a clock pulse, J and K inputs, and asked to describe the JK master-slave flip flop output.Homework Equations J K Q(t+1) 0 0 Q(t) No change 0 1 0...

Hi, I am looking to build some very simple state machines, with JK flip flops. I am planning to run them off a 9 volt battery, if that is feasible. Does anyone have a suggestion on what JK flip flop to buy, preferably from Mouser? I know Mouser has about 300 different parameters to pick...

Hi everybody... This is not actually a home work question...i didn't find any other place to post it... 1.Can we make master slave jk flipflop using 74LS73 ic's which containt two individual jk flipflops? 2.JK flip flop has two 3-input NAND gates and the outputs are fed back from its...

Homework Statement To create a mod counter using flip flops that counts from 5 down to 2 and repeats this cycle...example 5, 4, 3, 2, 5, 4, 3, 2, 5, 4, 3, 2... The Attempt at a Solution I currently can get it to count from 7 down to 2 no problems...the issue is...I don't know how to skip...

Hello forum. to make an LED blink, would I use a 555 chip or a flip flop and why? thanks fisico30

Hi, I am trying to understand and analyze JK flip flop's (using RS flop flop i.e. using NOR gates). I have written out the characteristic table and when I give Q = 1, J=1 and K = 0 I am trying to analyze the Q' (Q complement) by giving the intial state to 0. I find that Q settles to 1 (i.e...

Hi, I'm using DSCH3.5 and I'm trying to build a JK latch. I've found 3 different designs online (which confuses me) and I've recreated them in the software but they aren't functioning at all. Does anyone know what's going on? I'm losing a lot of sleep over this I must be doing something silly...

Please look @ the pictures below. I have drawn a master slave D flipflop with preset and clear option as mentioned in the book. http://i28.lulzimg.com/7e22bfc016.png Can anyone tell me what is the necessity of the wires that are highlighted in the image? isn't the wire @ last stages of...

when D will be 0 then in the first input to the lower nand gate will be 1 and the first input to the upper nand gate will be 0 If clock (CLK) = 1 then in the upper Nand gate 0 NAND 1 will be 1 and in the lower nand gate 1 NAND 1 will be 0. now In the Second upper NAND gate 1 will go as the...

[PLAIN]http://img713.imageshack.us/img713/853/98302269.jpg So I included the waveform I drew in the picture. The first one is the clock pulse, the second is the output from the T-flip flop on the left, and the third is the output from the T-flip flop on the right. I'm really not sure if this...

I had a lab and I wrote they are asynchronous, so the clock input matters, but I am starting to doubt if I did it properly :confused:...what is the effect for both suppose to be simultaneously or independently? Thanks.

j_k flip flop .by using vhdl ..please help hi every body i hope every things gana be okay i really have pro,,in my class so anyone can help me please give is hand to help any ways ,, my problem is about ,, my doctor give us homework about some things we don't know how to do , so...

Problem Statement: (a) Write a T-flip-flop description with a clock (clk) and a t input. Toggling is done on the rising edge of (clk) when t is '1'. Include a generic parameter for the flip-flop delay, one for minimum pulse width on t, and one for the flip-flop identification number. The...

I understand that the truth table involved, and how it works, but i don't get the timing of the diagrams. I've looked on numerous internet sites and through many books but i still don't understand how when J=K=0 and CLK= up, with Q having no change, that the out put (Q) is up, when the others...

Draw a D flip-flop using a T flip flop and combinational logic The Attempt at a Solution - I'm not even sure where to start with something like this. I'm trying to figure out how they relate and how you would be able to use one to draw the other. I know that in the standard design...

http://img329.imageshack.us/my.php?image=39501432oa1.jpg if one of them was 0 then no problem because the other wire value doesn't matter but here we have both 1 if i look on one of the NANDs gates we have one input of 1 and the other input value is unknown because it comes from the...

something has always bothered me about nand flip flops and their use in memory so I thought I would ask this here and get it cleared up. In a basic nand flip flop like the one found here: http://hyperphysics.phy-astr.gsu.edu/hbase/electronic/nandlatch.html#c1" I understand that there is a...

Homework Statement Does an edge triggered J-K master slave flip flop exist? In a clocked J-K master slave flip flop, the master may be positive edge triggered and the slave may be negative edge triggered or vice versa. Can this flip flop be called an edge triggered J-K master slave flip...

Homework Statement I am unable to understand the working of a positive edge triggered JK flip flop. In the figure, there are 2 AND gates on the left (one over the other) and there are 2 NOR gates on the right (one over the other). I have used an RS flip flop to construct the JK flip flop. The...

We're analyzing JK flip flop circuits and I don't understand it. So, Given that J = x, and K = xB' , my notes say that Q+ = JQ' + K'Q. I understand that. Then, substituting, we get xA' + x'A + xB. I have no idea how that final result was obtained. Can anyone help me with this?

In a flip-flop fluidic (air logic) device like the one shown in the attachment what happens if both the C1 and C2 are closed for the truth table.

for j k flip flop,there is a inverse clock,Q(output) , Q bar(knot) output ,J and K when drawing the timing diagram,is it necessary to state the output of the Q bar (knot) or only the Q (output) is enough?? pls help

does anybody knows how to read the table or has any explanation for jk flip flop??any website recommended pls...

Is latch a type of flip-flop? I'm confuse.

Given the table of a state diagram: Qpresent | Input | Qnext | Output 0 0 0 0 0 1 1 1 1 0 1 0 1 1 0 0 So, output = Qpresent' * Input I must use a JK flip flop implementation of all of this. I...