Understanding Flip-Flop Type D: Negative Edge Triggering and Delay Neglect

[Femme_physics]

Homework Statement

In the following drawing is given a intro signal to flip-flop type D, negative edge triggered. Also is given the clock pulse signal. Copy to your notebooks these signals and add intro signal Q. Presume that in starting condition Q=0. Also, neglect the delay times of the flop-flop

http://img688.imageshack.us/img688/594/flippys.jpg

Mine is the pencil of course. Does it make sense?

 

[I like Serena]

Hi!

Q remains 0 until the Cp pulse goes down.
At that time Q becomes and stays 1 (since the D signal is 1 at that time).


The D flip-flop stores the D signal at the negative edge of the clock pulse.

This means that when the clock pulse (Cp) goes down, the Q state changes.
Q becomes the state of the D signal at that time.

 

[Femme_physics]

Alright, as per your criticism...

http://img545.imageshack.us/img545/9672/gggraphs.jpg

The D flip-flop stores the D signal at the negative edge of the clock pulse.

What exactly is the negative edge of the clock pulse? Oh, you mean like when an AC current reaches negative current?

 

[I like Serena]

What exactly is the negative edge of the clock pulse? Oh, you mean like when an AC current reaches negative current?

The negative edge is where the clock pulse goes down (negative slope), which is the right side of the pulse.
AC current does not have a sharp edge like that.

The only place where Q can change is at that edge.

 

[LCKurtz]

From my hobby days I seem to recall that D flip-flops are rising edge triggered. Do they make them both ways now?

 

[I like Serena]

From my hobby days I seem to recall that D flip-flops are rising edge triggered. Do they make them both ways now?

According to wiki:
"The D flip-flop captures the value of the D-input at a definite portion of the clock cycle (such as the rising edge of the clock)."

Wiki seems to imply they are made both ways.
And the problem statement says it's the falling edge.

 

[Femme_physics]

The negative edge is where the clock pulse goes down (negative slope), which is the right side of the pulse.
AC current does not have a sharp edge like that.

The only place where Q can change is at that edge.

But the graphs only have positive edge?

 

[I like Serena]

But the graphs only have positive edge?

What do you mean by positive edge?

The graphs have both positive edges and negative edges.
Each pulse starts with a positive edge, also called the rising edge.
And each pulse ends with a negative edge, also called the falling edge.

 

[Femme_physics]

But I have both D and CP for reference. Now I know CP is the clock pulse. D is the input.

If Q can only change at NEGATIVE clock pulse edge, then I stand by my last diagram

 

[I like Serena]

But I have both D and CP for reference. Now I know CP is the clock pulse. D is the input.

If Q can only change at NEGATIVE clock pulse edge, then I stand by my last diagram

In your last diagram Q changes at the rising edge of the clock pulse...

EDIT: A negative edge does NOT mean that the signal is negative, but is means that the level of the signal goes down.

 

[NascentOxygen]

But the graphs only have positive edge?

The graphs are drawn to appear to have only positive levels, yes. But these waveforms are logic levels, not voltages, so they are never going to have negative levels. Logic is 1 or 0.

The transition from logic 0 to logic 1, denoted 0→1, is termed the "rising edge" or positive edge. When the logic level changes back to 0, the transition 1→0 is termed the "falling edge" or negative edge. (It has nothing to do with + or - voltages.)

Your Q output is so wrong that I suggest you erase it so you don't keep referring back to it, and can start again with a fresh outlook.

:::NEXT LINE EDITED::::
First step, trace the vertical dotted line from each clock pulse's 1→0 tranistion and mark these faintly on the Q graph--these mark the only place where the Q level can change logic levels because you are told that your D flip-flop is negative-edge triggered.

 

[Femme_physics]

http://img822.imageshack.us/img822/9113/9tcpq80t.jpg

Is this correct then?

 

[I like Serena]

Is this correct then?

Yep!

 

[Femme_physics]

Thanks :)

 

[Femme_physics]

*bumps*

Would my graph be any different if this was a positive edge triggered D-FF flip-flop, and not negative D-FF flip-flop?

 

[I like Serena]

*bump back*

Yes.
What do you think it would look like?

 

[Femme_physics]

I'm actually really confused about my answer from before.

According to the truth table of D flip-flops

When D = 1 and CLK = 1
then Q = 1

Since ours is negative on the first dotted line we still kept it zero. Ok.

On the second dotted line we have D = 1 and CLK = 0

That's "no change" on both Q and Q(capped)...yet we changed Q to "1" digital. Something doesn't add up here.

 

[NascentOxygen]

I'm actually really confused about my answer from before.

Hi FP! Confusion creeps in when you turn your back on a topic for a few weeks.

According to the truth table of D flip-flops

When D = 1 and CLK = 1
then Q = 1

Since ours is negative on the first dotted line we still kept it zero. Ok.

Yes, "ours" is negative-edge triggered, so the rising edge of the clock has no significance.

On the second dotted line we have D = 1 and CLK = 0

That's "no change" on both Q and Q(capped)...

Who says so? There is not really a "no change" input condition for the D.

yet we changed Q to "1" digital. Something doesn't add up here.

Yes, "we" changed Q to 1 because D was 1 at the crucial moment of the clock transitioning 1→0.

Review the D flip-flop here, though it's positive-edge triggered. http://www.doctronics.co.uk/4013.htm

 

[I like Serena]

Finally I have some time again to respond.
Sorry to keep you waiting.

I'm actually really confused about my answer from before.

According to the truth table of D flip-flops

When D = 1 and CLK = 1
then Q = 1

Ah, careful there.
You don't really have a "normal" truth table there with CLK being 0 or 1.

What they mean with CLK=1 is that the clock pulse "triggers".
And a trigger is that the clock pulse is on its edge.
In your new problem statement that is when the clock pulse rises.
At all other times it counts as CLK=0.

Since ours is negative on the first dotted line we still kept it zero. Ok.

On the second dotted line we have D = 1 and CLK = 0

That's "no change" on both Q and Q(capped)...yet we changed Q to "1" digital. Something doesn't add up here.

The first dotted line is a rising edge.
In the original problem statement that is not the trigger, so that counts as CLK=0.

At the second dotted line we have D=1 and we have a trigger since the clock pulse triggers on the falling edge.
So that counts as CLK=1!

 

[Femme_physics]

Ahh the truth table for "rising edge" and "falling edge" helped explain everything to me...

I basically only look at the places where it increases or falls (depends whether it's falling or rising) and then look at the corresponding truth table and bob's your uncle :)

Thanks Nascent, ILS! Though the test is behind me, I thought I aced it except possibly one issue (or two) that bothers me a bit (it's in electrical engineering forum).

 

[I like Serena]

Hey Fp!

Any tests left?
Or are you done for a while?

 

[Femme_physics]

Hi ILS!

Oh the big external electronics test is still ahead :) do u mind answering my Q at elecrical engineering forum with the PNP transistor? ( not in HW section )

 

[I like Serena]

Okay, I'll take a look (didn't notice you posting it).
Give me a minute... (or two ;)