Engineering Multiple input, multiple output circuit with only a signal getting through

[marianweb]

Hello

Can someone help me with this? I've been struggling with it for some time and haven't found a solution yet.
Let's say we have the circuit in the attachment. There is a number of inputs (4 in our case) and an equal number of outputs.

The problem is: if at least one input is HIGH, then one and only one output will be HIGH. And that one will correspond to the last activated input.
Fore example: let's say that only A(in) is 1. Then only A(out) will be 1. After some time, B(in) is also 1. Then B(out) will be 1, A(out) changing back to 0. If after some time D(in) is 1, then D(out) will be 1 and the other outputs will be 0. And so on...

Can someone tell me how this might be done? Have you encountered something similar until now?

 

[Proton Soup]

well, when one input goes high, its output is set, whilst the other outputs are reset. what do you think might do that?

 

[marianweb]

well, when one input goes high, its output is set, whilst the other outputs are reset. what do you think might do that?

:) well, it sounds familiar... But taking in consideration that fact that digital electronics is not my strong point, I really don't know.

 

[Proton Soup]

:) well, it sounds familiar... But taking in consideration that fact that digital electronics is not my strong point, I really don't know.

not mine, either. but i think i would start by trying to simplify the problem. like finding a solution for just one output, first. or maybe even limiting inputs to 2, initially. then go from there. if it's not a learning exercise, i think you can buy chips that do this function. and, flip-flops may not even be the preferred way to do this. you should be able to do it with straight logic gates, too. time to dig out those karnaugh maps.

 

[KGS]

You can solve this problem las it was said with simple flip-flop and RC circuit.
The reset signal can be generated from the input and it should be shorter in time than the input signal.
Let say A is triggered (High) when a new signal comes it should reset all the output so A will go to zero but since the coming signal is longer than the reset (that had been generated from the coming signal with RC) it will initialize the appropriate output.
I hope this will help you.
If not you have to clarify your question.