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N-P-N Transistor in Saturation Mode

  1. Jan 2, 2015 #1
    I don't understand the condition of saturation in an npn transistor (common emitter config). My textbook says that the collector-emitter voltage reduces to near zero upon increasing input voltage. Also, Wikipedia says that both BE and CE junctions 'become' forward biased. Can anyone please explain that? Thanks.
  2. jcsd
  3. Jan 6, 2015 #2


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    If you have a common-emitter amplifier set up, then you typically have the BE junction forward biased and the BC junction reverse biased (I think that's what you meant to write). Now, imagine the collector voltage goes to close to zero (maybe you have too big a resistor in the collector). Now, the BC junction has a diode drop across it as well. KVL around the loop shows Vce must be zero. That is saturation.
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