Need help analyzing and audio amplifier [final exam study guide]

[BenBa]

Homework Statement

Homework Equations

See Image

The Attempt at a Solution

I am confused where to start this problem. Obviously i need to get at the DC load line for Q1. But the problem is that I was taught in class that the DC load lines intercepts for a transistor are x-intercept Vcc and y-intercept Vcc/(Re+Rc). But Q1 has no Re OR Rc! So how am i supposed to find its y-intercept?!

Secondly I don't exactly know what open-loop voltage gain is, what is "open-loop" referring to? The voltage gain without the feedback loop? I am just unsure how to analyze the circuit like this?

Lastly, is by "closed loop gain" do they just mean the overall gain of this exact circuit?

Any help in guiding me through part a, b or c would be greatly appreciated!

 

[gneill]

Hi BenBa, Welcome to Physics Forums.

Homework Statement

Homework Equations

See Image

The Attempt at a Solution

I am confused where to start this problem. Obviously i need to get at the DC load line for Q1. But the problem is that I was taught in class that the DC load lines intercepts for a transistor are x-intercept Vcc and y-intercept Vcc/(Re+Rc). But Q1 has no Re OR Rc! So how am i supposed to find its y-intercept?!

Suppose Q1 is ON and near saturation. What will Q2 be doing under those conditions? What is the current path for Q1's Ic? Is there more than one path?

Secondly I don't exactly know what open-loop voltage gain is, what is "open-loop" referring to? The voltage gain without the feedback loop? I am just unsure how to analyze the circuit like this?

Yes, it's the voltage gain without the feedback path.

Lastly, is by "closed loop gain" do they just mean the overall gain of this exact circuit?

Yes.

Any help in guiding me through part a, b or c would be greatly appreciated!

Looks like you've got the gist of it.

 

[BenBa]

When Q1 is on an near saturation? Well aren't they in push-pull configuration? So whenever Q1 is ever on Q2 is off, i don't know what Q1 being near saturation entails...

 

[gneill]

When Q1 is on an near saturation? Well aren't they in push-pull configuration? So whenever Q1 is ever on Q2 is off, i don't know what Q1 being near saturation entails...

Yes, Q1 being on implies Q2 being off. So that eliminates one current path. Being near saturation implies that the transistor is as "on" as it can be. Now it could be that the overall circuit precludes the transistors being driven to saturation, but we're looking at the load line here, which has as its intercepts the extreme possibilities.

If the given transistor (BD139) is saturated, what's its collector-emitter voltage? That should tell you what the maximum possible potential is at the emitter...

 

[BenBa]

the collector emitter drop when Q1 is "as on as possible" is simply Vbe (Which is standard 0.7volts), right?

I think i just realized that the y intercept is at VCC/R4 because R4 is acting as the emitter resistor.

But why can we assume the transistor is "as on as possible"? Isn't the Q point somewhere in between?

 

[gneill]

the collector emitter drop when Q1 is "as on as possible" is simply Vbe (Which is standard 0.7volts), right?

Nope. But it will be in that neighborhood. Look up the characteristics of the transistor.

I think i just realized that the y intercept is at VCC/R4 because R4 is acting as the emitter resistor.

Is R4 the ONLY path for the emitter current?

But why can we assume the transistor is "as on as possible"? Isn't the Q point somewhere in between?

Yes, the operating point lies along the load line (usually somewhere in the middle). But the end points of the load line represent the extreme possibilities of circuit operation. They occur at saturation and cutoff.

 

[BenBa]

What characteristic of the transistor do i need to look at, our professor has never asked us to do that when the transistor is "as on as possible" so it it okay to assume it is essentially just 0.7?

Since this is DC analysis don't you cut off the Cout, so for the y intercept isn't the only place for the DC current to go through R4?

 

[gneill]

What characteristic of the transistor do i need to look at, our professor has never asked us to do that when the transistor is "as on as possible" so it it okay to assume it is essentially just 0.7?

Do a web search on "BD139 datasheet". You're looking for V_CE(sat). You should be able to locate the Fairchild Semiconductor datasheet PDF.

Since this is DC analysis don't you cut off the Cout, so for the y intercept isn't the only place for the DC current to go through R4?

Yes, Cout will be an "open" to DC. But is there anything else connected to the top of R4?

 

[BenBa]

Ah the feedback!

That looks so complicated though, i have no idea how to approach that because it feeds back into the op amp which then feeds back into the transistor..

 

[gneill]

What's the DC potential where the feedback resistor terminates?

 

[BenBa]

zero, because of the ideal op amp.

 

[BenBa]

so the current splits between R4 in paraallel with R2 which is in parallel with C1, this is complicated

 

[gneill]

zero, because of the ideal op amp.

Yes!

so the current splits between R4 in paraallel with R2 which is in parallel with C1, this is complicated

Is C1 relevant for DC?

 

[BenBa]

Gotcha! So the voltage is Vcc-Vsat-0.7 and there are two paths, but the current splits between R4 and R2. But we still don't know how much current is going out of the push-pull, right?

 

[gneill]

Gotcha! So the voltage is Vcc-Vsat-0.7 and there are two paths, but the current splits between R4 and R2. But we still don't know how much current is going out of the push-pull, right?

V_CE(sat) is the only potential drop of interest between the source +Vcc and the emitter (top of R4). It's the collector-emitter voltage.

If you know the potential at the top of R4 / R2 you can find the total current. Q2 is cut off, so no current there...

As you've already stated, R4 and R2 are essentially in parallel and thus comprise your R_E...

 

[BenBa]

So current out of the push-pull is equal to [Vcc-Vce(sat)]/[R4||R2] I get it!

But is this current also the same as the collector current for the Q point?

 

[gneill]

So current out of the push-pull is equal to [Vcc-Vce(sat)]/[R4||R2] I get it!

But is this current also the same as the collector current for the Q point?

No, this just establishes one end of the load line (for part (a) of the problem). The operating point will lie somewhere along that line. What conditions are usually applied to establish the operating point?

 

[BenBa]

So that i the y-intercept then? And we know our x-intercept is simply Vcc, right?

usually to establish the operating point after we know our intercepts we can write the equation i = \frac{-1}{R2||R4}Vce+\frac{Vcc-Vce(sat)}{R4||R2}

But we know neither the operating current or the operating Vce so we can't just plug one into get the other, do we assume that Vce is in the middle of the x-axis (Vcc/2) for maximum symmetric swing? Or can we not simply do that?

 

[gneill]

So that i the y-intercept then? And we know our x-intercept is simply Vcc, right?

For the load line y-intercept I just realized that you want to exclude the transistor from consideration (sorry about the Vsat digression, but at least it achieved the determination of the effective R_E). The y-intercept will just be Vcc/R_E since there's no R_C to add to it. It's the current that would result if the transistor were a perfect switch with zero V_CE.

usually to establish the operating point after we know our intercepts we can write the equation i = (-1/[R2||R4])*Vce+[Vcc-Vce(sat)]/[R4||R2].

But we know neither the operating current or the operating Vce so we can't just plug one into get the other, do we assume that Vce is in the middle of the x-axis (Vcc/2) for maximum symmetric swing? Or can we not simply do that?

The quiescent operating point occurs when the input signal to the overall amplifier is zero (assuming that the input would be a signal centered around zero). What current would you expect in the transistors when the input is zero?

 

[BenBa]

For the load line y-intercept I just realized that you want to exclude the transistor from consideration (sorry about the Vsat digression, but at least it achieved the determination of the effective R_E). The y-intercept will just be Vcc/R_E since there's no R_C to add to it. It's the current that would result if the transistor were a perfect switch with zero V_CE.

Can you explain this a little more, did I make a mistake? Is our y-intercept still Vcc/[R4||R2]?

The quiescent operating point occurs when the input signal to the overall amplifier is zero (assuming that the input would be a signal centered around zero). What current would you expect in the transistors when the input is zero?

The current in both transistors should be zero if input is zero right? Aren't both off when the Vin to the push-pull is zero? Or are they both on?

 

[gneill]

Can you explain this a little more, did I make a mistake? Is our y-intercept still Vcc/[R4||R2]?

No error, it's Vcc/[R4||R2].

The current in both transistors should be zero if input is zero right? Aren't both off when the Vin to the push-pull is zero? Or are they both on?

Rather than just tell you...

Consider the circuit conditions when the amplifier input is zero (grounded). The op-amp inputs are also at ground potential so the current through R1 is zero which means no current can flow through R2 either (where would it come from or go to?). What does that tell you about the potential at the R4 end of R2? In turn, what does that imply for the transistor currents?

(Note that the push-pull configuration precludes both transistors being on at the same time! The npn transistor requires a positive base bias (w.r.t. its emitter), while the pnp transistor requires the base to be biased negatively, and since their emitters are tied together and their bases tied to the same source, you can't have both turned on at the same time --- it's one or the other or neither).

 

[BenBa]

Sp this means when the base input is zero both transistors are off, correct? How does this help us find the operating voltage?

 

[gneill]

Sp this means when the base input is zero both transistors are off, correct?

Correct.

How does this help us find the operating voltage?

If the transistor is off, with its collector at +Vcc and its emitter at 0V, what is V_CE?

 

[BenBa]

The drop must be Vcc, but that is when it is non-operating, right? We still have yet to find anything that leads us to the Q-point of this transistor...i believe.

 

[gneill]

The drop must be Vcc, but that is when it is non-operating, right? We still have yet to find anything that leads us tot he Q-point of this transistor...i believe.

No, that's the point that it operates around. When quiescent (no input signal) it sits at the cutoff point. The other transistor does the same. In a push-pull configuration one transistor handles the positive excursions of the signal and the other the negative excursions.

 

[BenBa]

I apologize but i don't understand how this is the operating point if we were just considering the voltage drop when the transistor is off (not operating in my mind).

 

[gneill]

I apologize but i don't understand how this is the operating point if we were just considering the voltage drop when the transistor is of.

It's not that it's off that is the important thing. It just happens to be off at its operating point. It's where the transistor in this case "idles" when there's no signal applied to the circuit. If you think about it, this makes the circuit very efficient since no current is drawn by the transistors with no signal applied. This is quite different from the case of the common emitter single transistor amplifier where the transistor must be biased to to some point in the middle of the load line so that it can handle both positive and negative swings of the input, and so draws current even when no signal is present.

 

[AlephZero]

But we know neither the operating current or the operating Vce so we can't just plug one into get the other, do we assume that Vce is in the middle of the x-axis (Vcc/2) for maximum symmetric swing? Or can we not simply do that?

So far, you have been figuring out what happens to Q1 when it is on. Don't forget the output stage also has Q2.

So far, you have been thinking about what happens when the output of the op-amp stage is a positive voltage. Now think about what happens when it is negative.

 

[BenBa]

So is this an accurate image of what the two Load lines look like?

It's not that it's off that is the important thing. It just happens to be off at its operating point. It's where the transistor in this case "idles" when there's no signal applied to the circuit. If you think about it, this makes the circuit very efficient since no current is drawn by the transistors with no signal applied. This is quite different from the case of the common emitter single transistor amplifier where the transistor must be biased to to some point in the middle of the load line so that it can handle both positive and negative swings of the input, and so draws current even when no signal is present.

I guess i never truly understood what the Qpoint was. I always just assumed that it was the collector current and Vce drop that the transistor "wants" to maintain when it is currently turned on.

 

[gneill]

Yes, the images look okay to me.

The Qpoint is where on load line the transistor "sits" when the circuit is idle (no input signal).

 

[BenBa]

Isn't that a poor Qpoint because it is near the edge, so any amount of swing in one direction of input will cause the transistor to hit the rail. I was told that good transistors have Qpoints in the center of the line for maximal symmetric swing.

EDIT: or is it a perfect Q point because it means that when the voltage in is positive only one transistor is on and vice versa for negative voltage?

 

[gneill]

Isn't that a poor Qpoint because it is near the edge, so any amount of swing in one direction of input will cause the transistor to hit the rail. I was told that good transistors have Qpoints in the center of the line for maximal symmetric swing

That is a concern for single transistor amplifiers. This is a push-pull configuration. When one transistor "hits the rail", the other is just beginning to turn on and take over. Each transistor handles half of the signal (assume a sinusoidal input for simplicity). As a result, theoretically they can both access their entire load lines to handle their half of the signal. A single transistor configuration must handle the entire signal on its single load line.

 

[BenBa]

Awesome that makes so much sense!

Okay so now to get the open loop voltage gain. We just need to ignore the feedback resistor and capacitor and put in a signal and find out what happens to it.

Here is what i think, the input will either be positive or negative (or zero) so only one transistor will be on at a time, so we just need to find the gain from the push pull amplifier from one transistor.

But wait, if it's open loop and the inputs of the op amp are pinned at zero (because its ideal V+ = V-) then shouldn't all of Vin be lost over the first resistor? What does this mean for the output of the op amp?

 

[gneill]

If you cut the feedback loop, the mechanism that keeps the op-amp inputs potential difference at (essentially) zero is removed too...

 

[BenBa]

I thought that the mechanism that kept the op amp inputs both at zero was a property of ideal op amps. Meaning that the inputs are both still held at zero because the plus terminal is at ground. Doesn't this imply that the voltage must drop to zero from Vin over just R1? How does that effect the output of the op amp?

 

[gneill]

I thought that the mechanism that kept the op amp inputs both at zero was a property of ideal op amps. Meaning that the inputs are both still held at zero because the plus terminal is at ground. Doesn't this imply that the voltage must drop to zero from Vin over just R1? How does that effect the output of the op amp?

The mechanism is the very high gain of the op-amp coupled with the feedback loop. Without the feedback loop the ideal op-amp is just a differential amplifier with infinite gain... A "real" op-amp is a differential amplifier with very, very high gain whose output is limited by the supply rails.

 

[BenBa]

The mechanism is the very high gain of the op-amp coupled with the feedback loop. Without the feedback loop the ideal op-amp is just a differential amplifier with infinite gain... A "real" op-amp is a differential amplifier with very, very high gain whose output is limited by the supply rails.

So without the feedback loop in there the output of the op amp is it's rail voltage? Would that be +15 volts? Or -15Volts? Or does it depend on the input at all?

 

[gneill]

So without the feedback loop in there the output of the op amp is it's rail voltage? Would that be +15 volts? Or -15Volts? Or does it depend on the input at all?

It'll be pinned to one rail or the other depending upon the polarity of the input signal, and it can be a very minute signal. In a perfect circuit you might expect the op-amp output to be zero if you grounded the input. But in the real world op-amps aren't perfect and suffer noise and offset currents and voltages. Random noise could set the amplifier bouncing between the rails if the input was open or grounded, or perhaps it would be pinned to one rail in particular due to these imperfections. It's tricky to design practical op-amp circuits lacking feedback.

 

[BenBa]

So for the purposes of getting gain let's assume that the op amp pins the voltage at +15, that means the Q1 is active, so how do we get the gain of the push pull amplifier? we know Vb is 15 volts except it has to drop across R3...

Or is the gain of the circuit infinite since it takes infinitesmally small amount of voltage to get a gain of something clearly large?

 

[gneill]

So for the purposes of getting gain let's assume that the op amp pins the voltage at +15, that means the Q1 is active, so how do we get the gain of the push pull amplifier? we know Vb is 15 volts except it has to drop across R3...

Or is the gain of the circuit infinite since it takes infinitesmally small amount of voltage to get a gain of something clearly large?

The gain will be very large since the op-amp will pin its output and cause the maximum drive the circuit is capable of to the transistors (either positive or negative) for very tiny input signals. You might determine an order of magnitude from the typical open-loop gain of the op-amp specified (look up the device characteristics). Also be sure to specify the sign of the amplification.

 

[BenBa]

The gain will be very large since the op-amp will pin its output and cause the maximum drive the circuit is capable of to the transistors (either positive or negative) for very tiny input signals. You might determine an order of magnitude from the typical open-loop gain of the op-amp specified (look up the device characteristics). Also be sure to specify the sign of the amplification.

Sorry i don't quite understand.
So the Open loop gain of the LF411 is just above 100,000. So clearly the input of the transistors is pinned at 15V (absolute value), but how does the push pull amplifier behave at this voltage? I assume it amplifies it even more, right? Or is the gain from that negligible compared to that of the op amp?

Also what exactly is feedback fraction? How can we have a feedback fraction if it's open loop, or is this asking us about the original circuit again?

 

[gneill]

Sorry i don't quite understand.
So the Open loop gain of the LF411 is just above 100,000. So clearly the input of the transistors is pinned at 15V (absolute value), but how does the push pull amplifier behave at this voltage? I assume it amplifies it even more, right? Or is the gain from that negligible compared to that of the op amp?

You'll have to determine whether or not it's negligible. With a tiny enough input signal the output of the op-amp can (theoretically) be kept between the rails, even open-loop. Given a gain of 100,000 for the op-amp, what input voltage would just bring the op-amp output to a rail? When the op-amp is at the rail, what is the output voltage of the push-pull section?

Also what exactly is feedback fraction? How can we have a feedback fraction if it's open loop, or is this asking us about the original circuit again?

If memory serves, for a closed-loop amplifier the feedback fraction is the reciprocal of the closed-loop gain when the open-loop gain is very large.

I'm not sure whether they are asking (B) about the open or closed loop case. If it's open-loop then no portion of the output is fed back as you have surmised, in which case the answer is trivial. If it's closed-loop then that's a different matter. I wonder if they're still talking about the DC conditions, too. The feedback fraction would change with frequency (thanks to the capacitor in the feedback path).

 

[BenBa]

You'll have to determine whether or not it's negligible. With a tiny enough input signal the output of the op-amp can (theoretically) be kept between the rails, even open-loop. Given a gain of 100,000 for the op-amp, what input voltage would just bring the op-amp output to a rail? When the op-amp is at the rail, what is the output voltage of the push-pull section?

I see, just from some quick math if the input voltage(absolute value) is less than 150 microVolts it will be between the rails. Noise is approximately on that level, i think its fair to assume for this problem that it hits rail voltage.

OH duh! Push pull amplifiers only amplify current not voltage!

If memory serves, for a closed-loop amplifier the feedback fraction is the reciprocal of the closed-loop gain when the open-loop gain is very large.

I'm not sure whether they are asking (B) about the open or closed loop case. If it's open-loop then no portion of the output is fed back as you have surmised, in which case the answer is trivial. If it's closed-loop then that's a different matter. I wonder if they're still talking about the DC conditions, too. The feedback fraction would change with frequency (thanks to the capacitor in the feedback path).

I believe they must be asking about the closed loop case, or else it would be trivial. If the feedback fraction is just the reciprocal of the closed-loop gain when open loop gain is very large (which it seems to be) doesn't that mean it does not vary with frequency?

And how do we find out the closed-loop gain? I know that since the push-pull only amplifies current we are just looking for the gain of the op amp and normally inverting op amps have a gain of -R2/R1 but does this hold when the feedback loop doesn't occur until the all the way after the push-pull amp, and how do we account for the capacitor?

 

[gneill]

I see, just from some quick math if the input voltage(absolute value) is less than 150 microVolts it will be between the rails. Noise is approximately on that level, i think its fair to assume for this problem that it hits rail voltage.

OH duh! Push pull amplifiers only amplify current not voltage!

Push-pull amps are great for achieving large output currents, but there will still be an output voltage.

Open loop, only R4 is in the emitter paths of the transistors and the output voltage will be developed across it. You should be able to estimate the output voltage that occurs when the voltage driving the push-pull stage is ± 15V.

I believe they must be asking about the closed loop case, or else it would be trivial. If the feedback fraction is just the reciprocal of the closed-loop gain when open loop gain is very large (which it seems to be) doesn't that mean it does not vary with frequency?

The closed-loop gain will vary with frequency due to the capacitor in the feedback path (But by how much?). It would be helpful to know what effect the capacitor has on the gain over the given frequency range.

This question can be either relatively simple to answer or rather more complicated... you'll have to be the judge based on the material in the course section that this problem comes from.

Unless your text defines some particular conditions for determining the gain of an audio amplifier (input signal voltage and frequency, amplifier load), my suggestion would be to look at the low frequency (f → DC) gain to answer the problem. That would be the simple version.

And how do we find out the closed-loop gain? I know that since the push-pull only amplifies current we are just looking for the gain of the op amp and normally inverting op amps have a gain of -R2/R1 but does this hold when the feedback loop doesn't occur until the all the way after the push-pull amp, and how do we account for the capacitor?

It holds for the whole amplifier, too. The op-amp will drive the push-pull stage with whatever amount of voltage required so that feedback will null the voltage difference between its inputs. Effectively, the push pull stage becomes the new output stage of the op-amp. (you could draw a bigger triangle and include the push-pull stage inside and call that your op-amp!)

The feedback loop is a filter thanks to the capacitor in the path, so the gain will vary with frequency. The only question is by how much? Check to see what effect it will have at either extreme of the signal frequency range (20 Hz - 20 kHz). How does the capacitor impedance compare to R2 for those frequencies?

 

[BenBa]

Push-pull amps are great for achieving large output currents, but there will still be an output voltage.

Open loop, only R4 is in the emitter paths of the transistors and the output voltage will be developed across it. You should be able to estimate the output voltage that occurs when the voltage driving the push-pull stage is ± 15V.

Are we to again assume that no current flows in the base (meaning there is no drop of voltage across the base resistor? If so it is not a hard calculation because it is 15-0.7. I'm not sure how to calculate it if we can't assume the above.

The closed-loop gain will vary with frequency due to the capacitor in the feedback path (But by how much?). It would be helpful to know what effect the capacitor has on the gain over the given frequency range.

This question can be either relatively simple to answer or rather more complicated... you'll have to be the judge based on the material in the course section that this problem comes from.

Unless your text defines some particular conditions for determining the gain of an audio amplifier (input signal voltage and frequency, amplifier load), my suggestion would be to look at the low frequency (f → DC) gain to answer the problem. That would be the simple version.

This is an introductory course and the professor very barely went over feedback. So i think it's a fair assumption to take the easier route.

So when frequency goes to DC the capacitor acts as an open circuit and we simply have feedback through R2. I know that for an inverting op amp the closed loop feedback gain is -R2/R1 but that is when the feedback loop is taken right after the output of the op amp, in this scenario we have an output resistor, a push-pull amplifier, and a resistor to ground all before the feedback loop starts, so how do i factor those into the feedback?

It holds for the whole amplifier, too. The op-amp will drive the push-pull stage with whatever amount of voltage required so that feedback will null the voltage difference between its inputs. Effectively, the push pull stage becomes the new output stage of the op-amp. (you could draw a bigger triangle and include the push-pull stage inside and call that your op-amp!)

Does this mean i don't need to take R3 into account for the feedback loop of the op amp? But i still have to deal with R4 affecting the feedback loop, right?

The feedback loop is a filter thanks to the capacitor in the path, so the gain will vary with frequency. The only question is by how much? Check to see what effect it will have at either extreme of the signal frequency range (20 Hz - 20 kHz). How does the capacitor impedance compare to R2 for those frequencies?

I am not sure how to "plug in" different frequencies into the circuit to check what happens. I know that the capacitor has impedance 1/jωC so the impedance gets larger with lower frequencies, but how do we account for this in the feedback loop to get a gain?

 

[gneill]

Are we to again assume that no current flows in the base (meaning there is no drop of voltage across the base resistor? If so it is not a hard calculation because it is 15-0.7. I'm not sure how to calculate it if we can't assume the above.

KVL and the relationship between I_B and I_C or I_E via β. Assume β = 100, and V_BE = 0.7V, or look up values for the particular transistor. Solve for the emitter current.

This is an introductory course and the professor very barely went over feedback. So i think it's a fair assumption to take the easier route.

So when frequency goes to DC the capacitor acts as an open circuit and we simply have feedback through R2. I know that for an inverting op amp the closed loop feedback gain is -R2/R1 but that is when the feedback loop is taken right after the output of the op amp, in this scenario we have an output resistor, a push-pull amplifier, and a resistor to ground all before the feedback loop starts, so how do i factor those into the feedback?

You can "move" R4 out beyond the feedback connection point if you wish, it's all one node and where things connect to it don't matter. The added stage is encompassed by the feedback loop, so you can pretend it's part of the op-amp. The op-amp will drive that stage to accomplish its "mission".

Does this mean i don't need to take R3 into account for the feedback loop of the op amp? But i still have to deal with R4 affecting the feedback loop, right?

Yes, ignore R3 and everything else associated with anything "before" the feedback pick-off point. Ignore R4 too! The op-amp will DO ANYTHING to accomplish the requirements of the feedback in nulling the voltage difference at the inputs of the op-amp. This includes forcing the output stage to drive enough current to supply any load, just so long as the feedback requirements are met.

I am not sure how to "plug in" different frequencies into the circuit to check what happens. I know that the capacitor has impedance 1/jωC so the impedance gets larger with lower frequencies, but how do we account for this in the feedback loop to get a gain?

Compare the magnitudes of the capacitor impedance at the two frequency endpoints with the value of R2. Will it make a significant difference? If you wish you can solve for the parallel impedance of C1 || R2, call it Z2, then write the gain as -Z2/R1. Plot |Z2/R1| versus frequency.

EDIT: Fixed resistor number (red)

 

[BenBa]

I can't think of a good KVL loop to use because the op amp gets in the way of any loop i try to create.

I am having trouble comparin magnitudes of capacitor impedance because they are imaginary...

What is the purpose of plotting Z2 over R2 vs frequency? Did you mean Z2 over R1?

 

[gneill]

I can't think of a good KVL loop to use because the op amp gets in the way of any loop i try to create.

The op-amp looks like a 15V source if it's pinned at the top rail. So:

You might need a touch of KCL, too.

I am having trouble comparin magnitudes of capacitor impedance because they are imaginary...

Magnitudes are never imaginary. How do find the magnitude of a complex value?

What is the purpose of plotting Z2 over R2 vs frequency? Did you mean Z2 over R1?

Sorry, I meant R1 of course. It was a typo, and I've fixed it in my post now. Thanks for pointing it out. You want to see how the gain behaves across the frequency range of the amplifier.

 

[BenBa]

So we have 15V - I_3R_3 - V_{be} - I_{Q1e}R_4 = 0
and we have I_3 + I_{Q1c} = I_{Q1e}

But since I_{Q1c} = I_{Q1e} right? But i don't think we can assume that because that would imply I3 is zero.

 

[gneill]

So we have 15V - I_3R_3 - V_{be} - I_{Q1e}R_4 = 0
and we have I_3 + I_{Q1c} = I_{Q1e}

But since I_{Q1c} = I_{Q1e} right? But i don't think we can assume that because that would imply I3 is zero.

The emitter current is the sum of the base and collector currents (KCL). The collector current is β times the base current, or alternatively, the emitter current is (β+1) times the base current. A common assumption is β = 100.