module fsm(input clk, rst, fifty, onedollar,
output insert, dispense, reject);
reg [1:0] st;
wire [1:0] nst;
parameter ready = 2'b00, s1 = 2'b01, dispense = 2'b10, reject = 2'b11;
always@(posedge clk) begin
if ~rst st=ready;
else st=nst;
end
assign...