Leakage current with NAND gates and pull-up resistor: Yes or No?

Thread starter EvLer
Start date Sep 11, 2005
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Current Leakage

AI Thread Summary

When using NAND gates with a pull-up resistor, there is a potential for leakage current, particularly when one NAND gate is in a high-high (HH) state and the other in a low-low (LL) state. A circuit diagram would clarify the setup, but the key point is that the datasheet confirms the presence of leakage current in this configuration. Understanding the implications of this leakage is crucial for circuit design. The discussion emphasizes the importance of consulting datasheets for accurate information on current behavior. Overall, leakage current is a relevant factor when designing circuits with NAND gates and pull-up resistors.

Sep 11, 2005

EvLer

Let's say I have two NAND gates hooked up to a pull-up R and an inverter.
If one NAND has HH input and the other LL, would there be a leakage current into LL input state gate?

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Sep 12, 2005

Manchot

It would be helpful to show us a circuit diagram. The way you have it worded, it doesn't really make all that much sense.

Sep 12, 2005

EvLer

nvmd, i think i got it.
There is a leakage current, the datasheet says so

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