Engineering Thévenin resistance when branch is 0V (RC circuit)

[mabster]

Homework Statement

Prior to t=0, switch is in position A (for long time).
Afterward, switch is in position B.

We need to derive the equation for v_c.

Homework Equations

v(t)=v(\infty)+[v(0)-v(\infty)]e^\frac{-t}{\tau}
\tau=RC

The Attempt at a Solution

at t=0: v(0)=100\frac{10}{10+15}=40\,\mathrm{V}
at t=\infty: v(\infty)=0\,\mathrm{V} since no current travels through open-circuit at capacitor.

R=R_\mathrm{th}=(15+10)\parallel 100=20\,\mathrm{k\Omega}

From here, I would simply substitute the values in.

My problem is that this thévenin resistance is wrong (the correct value being 100 kΩ). I was told that it has to do with the entire bottom of the circuit being at 0 V relative to the 100 V, so the left hand loop of the circuit is disabled. I was hoping someone could give me a less hand-wavy reason that this would be the case?

 

[phinds]

what makes you think that a capacitor with no current going through it has to have 0v across it?

 

[mabster]

Under steady-state condition (t=\infty), the capacitor will act as an open-circuit.

KCL at B: I_1=-0, so I_1=0\,\mathrm{A}
KVL around right-hand loop: v_c(\infty)=I_1(100\times 10^3)=[0](100\times 10^3)=0\,\mathrm{V}

I'm not sure if there's typically a differential equation argument for this, but we don't use DE to solve these in my particular course.

Have I made a mistake at this point?

 

[gneill]

My problem is that this thévenin resistance is wrong (the correct value being 100 kΩ). I was told that it has to do with the entire bottom of the circuit being at 0 V relative to the 100 V, so the left hand loop of the circuit is disabled. I was hoping someone could give me a less hand-wavy reason that this would be the case?

When the switch is in position B the capacitor and 100K resistor are alone in a loop. There is no complete circuit (closed loop) that would place the 10K and 15K resistors in any shared current path or potential difference. A single wire connection (i.e. the bottom rail reference node) does not make a complete circuit.

So once the switch moves to position B, it's as thought the voltage source and its resistors simply vanish as far as the capacitor and 100K resistor are concerned.

 

[phinds]

Under steady-state condition (t=\infty), the capacitor will act as an open-circuit.

KCL at B: I_1=-0, so I_1=0\,\mathrm{A}
KVL around right-hand loop: v_c(\infty)=I_1(100\times 10^3)=[0](100\times 10^3)=0\,\mathrm{V}

I'm not sure if there's typically a differential equation argument for this, but we don't use DE to solve these in my particular course.

Have I made a mistake at this point?

I was responding purely to your statement

... v(∞)=0V since no current travels through open-circuit at capacitor.

as thought it was a general statement without regard to the circuit, which is what it sounded like to me.

The point of the circuit, as gneill has already pointed out, is that the cap is charging in one circuit, discharging in a different circuit.

 

[mabster]

... v(∞)=0V since no current travels through open-circuit at capacitor.

as thought it was a general statement without regard to the circuit, which is what it sounded like to me.

Thanks, that's a really good point phinds! That's the kind of thing that will lose marks during the exams. I'll need to curb that :) !

Much appreciated!

 

[mabster]

A single wire connection (i.e. the bottom rail reference node) does not make a complete circuit.

Thanks! What you're saying makes sense, but I'm still missing the "intuition" here (this seems so fundamental that I should already know this). My problem is that the bottom rail is electrically common, so this should be an equivalent circuit:

Which to me would act like resistors in parallel.

I've tried to simulate the original circuit on http://www.falstad.com/circuit/" (not sure how accurate that is) and it does appear that no current travels across the rail.

I'm close, but still a little confused :)

 

[gneill]

Drawn the way you have it the "rail" sits between two loops. That's fine. It's zero voltage, zero resistance characteristic erects an impenetrable barrier between the loops; they cannot see each other. Nothing that happens in one loop will be seen by the other because the wire "shorts out" any voltage changes, and a zero resistance wire can carry any amount of current without creating a voltage drop.

 

[mabster]

Brilliant! That all makes sense to me now!

Thanks heaps!