# Amplifier circuit

#### zsolt2

1. The problem statement, all variables and given/known data
Hi all.
I need a bit help with the following.
Estimate the power developed in the 8 Ω speaker of the circuit of FIGURE 2 for a 1 kHz sinusoidal input signal of 100 mV peak. All capacitors may be assumed to act as a short circuit at the frequency of operation.
Compare your estimate with that derived from a PSpice simulation.
(I uploaded a picture of the circuit)

2. Relevant equations
Gv common emitter= Rc/Re , Gv emitter follower ~1 , power developed (Vrms^2)/R

3. The attempt at a solution
The gain of the first stage(common emitter):
as the 47 ohm resistor is not bypassed the gain becomes 0.1x1000/47=2.127V
As the question is only wants an estimate the second stage (emitter folower) can be estimated to have a gain of 1. So the peak voltage in the speaker is ~2.127V
to get the power developped I need the rms voltage which is 1.5V
and the power is 1.5^2 /8 =0.281= 281mW
But when I look at the PSpice simulation it differs:
the voltage by the output of the first stage is ~1.5V and the voltage in the speaker is a peak ~1.4
and the power developed in it is 245mW peak and 150mW rms
Can you help me where am I wrong?
Thank you!

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#### berkeman

Mentor
The gain of the first stage(common emitter):
as the 47 ohm resistor is not bypassed the gain becomes 0.1x1000/47=2.127V
As the question is only wants an estimate the second stage (emitter folower) can be estimated to have a gain of 1. So the peak voltage in the speaker is ~2.127V
to get the power developped I need the rms voltage which is 1.5V
and the power is 1.5^2 /8 =0.281= 281mW
I agree with this approach, but be careful not to call 0.1x1000/47 the "gain" of the first stage. The "gain" of the first stage is -1000/47, and you have multiplied by the peak input voltage to get the peak output voltage. Your calculation is okay, I would just call it the calculation of the peak output voltage of the first stage. The "-" sign is not important in this problem, so maybe that's why you omitted it.

As for the simulation, since PSPICE does not have "ideal" capacitors as elements, what values did you use for the capacitors? I'm guessing that's why you are getting a lower gain out of the simulation. Can you check the gain through the first stage to see if it's -1000/47 as expected?

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#### zsolt2

Thanks for your answer. I remembered that I forget to add re to the equation which is hie/hfe.
(a data sheet was given to this assessment).
For this transistor hie=5.5kohm and hfe=370
so re= 5500/370=14.86
The gain of the circuit is then 1000/(47+14.86)=16.16
So the output signal of the first stage is
0.1x16.16=1.619V
Using the same assumption as before for the emitter follower stage gain ~1
Peak voltage in speaker is ~1.616V
That is much closer to the PSpice one and I assumed that the emitter follower has unity gain which is more likely to be around 0.9
The only thing I am not sure now is that the rms voltage or the peak voltage needed to be to calculate the power?
I can't remember the capacitor values exactly but if I am right
Input capacitor for the first stage is 10uF
Bypass capacitor 200uF
The capacitor joining the stages 10uF
And the output capacitor is 100uF

#### zsolt2

Oh and the gain of the common emitter stage in the PSpice circuit is 15

#### Tom.G

More things to consider:
Load on the first stage (it is driving more than just the collector resistor)
hoe of 1st stage
Emitter resistance of the output stage

#### zsolt2

I know what you mean by that, but the data sheet I was given to the assignment doesn't contain the value oh hoe, nor the hie of the BFY51 transistor (the second one, hie2), so I am unable to calculate the load on the first stage as the hie of the combine transistors is hfe1 x hie2. For the same reason I cannot calculate the exact gain of the emitter follower.
As the assignment only asks for an estimate I assumed that hoe is very large and can be ignored (used this assumption through the module) and also that the emitter follower stage has unity gain

#### Tom.G

the data sheet I was given to the assignment doesn't contain the value oh hoe, nor the hie of the BFY51 transistor (the second one, hie2), so I am unable to calculate the load on the first stage
Ok, fair enough. The hoe only contributes a few percent error. What about the base bias network for the second stage?

#### berkeman

Mentor
I know what you mean by that, but the data sheet I was given to the assignment doesn't contain the value oh hoe, nor the hie of the BFY51 transistor (the second one, hie2), so I am unable to calculate the load on the first stage as the hie of the combine transistors is hfe1 x hie2.
Is a better model available for PSPICE for this transistor? If not, how about just using a jellybean NPN transistor that could be used in this application? (like a 2N3904)

#### zsolt2

Is a better model available for PSPICE for this transistor? If not, how about just using a jellybean NPN transistor that could be used in this application? (like a 2N3904)
No, I can't use any other model

#### zsolt2

Ok, fair enough. The hoe only contributes a few percent error. What about the base bias network for the second stage?
The 8.2 and18 k resistors are forming a pot divider:
12x 18000/(8200+18000)=8.244V at Vb
Ther is about 1.4V drop in the Darlington pair,
so volt across 27ohm resistor
8.244-1.4=6.84V
So the output voltage is
12-6.84=5.16
In the simulation it comes out to 6.12V
But I don't know how does it help me?

#### LvW

2. Relevant equations
Gv common emitter= Rc/Re ,

3. The attempt at a solution
The gain of the first stage(common emitter):
as the 47 ohm resistor is not bypassed the gain becomes 0.1x1000/47=2.127V
1) At first, a general remark:
In electronics, no formula is correct by 100% because we always neglect some minor influences. Hence, each expression is an approximation which - more or less - for a specific application can be regarded as sufficiently exact. That means: Applying a formula, we must be sure that the "surrounding conditions" allow the usage of the formula.

2) Your circuit: For the common emitter stage you have used the expression G=-Rc/Re .
What will happen for Re=0? G approaching infinity ? No - of course not!
Are you aware that this rough approximation may be used only under the condition Re>>1/gm ?
Here is the "exact" gain expression: G=-Rc/[(1/gm)+Re].

I think, in your case, the inverse transconductance 1/gm=Vt/Ic must not be neglected against Re=47 ohm.
Hence, as a first step it is necessary to find the DC quiescent current Ic.
This will be one reason for the discreapency between your calculation and Simulation.

Remark: Of course, during calculaton you have to consider the fact that the first stage is loaded by the second stage (the input resistance of the 2nd stage is in parallel to Rc)

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#### zsolt2

Sorry I put the wrong formula in the equations box
I used Gv=-Rc/(Re+re)
Where re is hie/hfe in this case
5500/370
Is that sounding better?

#### LvW

Where re is hie/hfe in this case
5500/370
Where are these values coming from? Do you know the DC operating point (Ic) ?

#### zsolt2

Where are these values coming from? Do you know the DC operating point (Ic) ?
There is a data sheet given to the assignment that's where I got hie and hfe

#### LvW

There is a data sheet given to the assignment that's where I got hie and hfe
But hie strongly depends on the actual DC operating point.....

My calculation: Ic~5.5mA re=Vt/Ic~4.7 ohms
Gain of the first stage (second stage connected): G=850/(47+4.7) ~ 16.4
(Simulation 16.3)

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#### zsolt2

But hie strongly depends on the actual DC operating point.....

My calculation: Ic~5.5mA re=Vt/Ic~4.7 ohms
Gain of the first stage (second stage connected): G=850/(47+4.7) ~ 16.4
(Simulation 16.3)
My calculation shows 16.16 which is a good estimation (although it could be a coincidence and the equation I used wrong)
How did you calculate the input impedance of the second stage?
The only equation I know to get it is
Rb||(hie+Roc(1+hfe))
Where Rb=8.2k||18k and Roc=27||8
But hie is not given for the second transistor and the equation to calculate it is not in the module?!? Also what is Vt in your calculation?

#### Merlin3189

Homework Helper
Gold Member
I never thought I'd agree with LvW, but his point 1 is central to any circuit calculation for me.
Where of course I depart from him, is in his point 2. As he himself notes, even the "exact" formulae are subject to point 1 again. You can get iteratively better as you put in more effort to the calculation. But isn't that what programs like Spice are for?

When I read "estimate", I did just that. After scanning the cct to see that it is a very basic, almost idealised, cct, I agreed with OP's basic formula.

So Rc about 1k and unbypassed Re 47 R, both presumably ± 10% or even 20%, gives a gain of 20+ and the emitter follower 1-, for an overall gain of 20 give or take.
That's convenient because Vp = 2 V gives (Vr)2 = 2 V2 and so P = 2/8 = 250 mW

That's what I think of as estimating.

I'm amazed to find that PSpice gave 281 mW, only 12.4% higher. I'd have been happy with anything from 200 - 300 mW.

Would we expect the real cct to be much closer to the PSpice value? (Not rhetorical. I don't use Spice myself, so I wonder how it works out in practice.)

#### LvW

The calculation of the actual DC current Ic for the first stage is based on two unknown (and only estimated) parameters (Vbe=0.7 V and beta=Ic/Ib).
Therefore, it makes no sense (and is good engineering practice) not to be as exact as possible for the second stage.
Hence, I have used only the resistive voltage divider (18k||8k) for the 2nd stage input resistance.
I think, for an emitter follower this is a sufficient approach.
(By the way: In your formula, the parameter hfe is the current gain for the Darlington combination, which is the product hfe1*hfe2.)

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#### LvW

I never thought I'd agree with LvW, ..
To me, this sounds surprising.
May I kindly ask you to explain, why you didnt expect to agree with me in some respect?

Where of course I depart from him, is in his point 2.
Of course ? I think, this statement deserves some explanations.
I have quoted the well-known gain expression for the common emitter stage with feedback - as can be found in each relevant textbook.
Something wrong?
I kindly ask you again to explain why you "depart" from me in this respect.
Let me explain my position:
As soon as I see that the transistor has an effective feedback resistor, I use the formula which includes the feedback effect, of course.
And only as a second step I can decide (after having evaluated its influence on the gain value) if it makes sense to consider the inverse transconductance re=1/gm or not.
In my answer, I have stated that this rough approximation (Rc/Re) may be used only under the condition Re>>1/gm ?
And you cannot follow me? Are you able to see from the beginning if this condition can be met or not ?
Are you aware that - for a Dc current Ic=1mA - the term you propose to neglect would be app. 50% of the effective feedback resistor?
Are you really able to see by a simple visual inspection of the circuit that the DC current will be larger than 5 mA?
Please tell me, what is wrong with my approach?
Thank you.

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#### zsolt2

Thank for all of your help!

#### Merlin3189

Homework Helper
Gold Member
Yes, of course (again!) you (LvW) can ask.
I would not expect to agree with you. It's not intended as a criticism, but a difference between our approaches, since your knowledge of these things is MUCH greater than mine. Whereas you can, and often do, use exact equations to analyse circuits, I as an amateur in these things am accustomed to rules of thumb and rough and ready calculations.
As I said, I saw this question as asking for a simple analysis, then an appreciation of the factors that a more detailed calculation by Spice can take into account.

The second "of course" about departing from your point 2, is really the same. You see his answer and start applying much more careful analysis to try to get closer to the Spice model result. I just thought, yes, he's used a fair approximation and got an answer which is near enough.
I don't depart from your analysis, I depart because I wouldn't have bothered to do it.

So I'm not saying your analysis is wrong. On the contrary I am interested to follow your working (sometime I might want to do more thorough analyses) and you have not said anything I would disagree with. Indeed I was struck by the low value you showed for re of ≈ 4.7 R, because even if I'd made a correction for this, I'd have guessed (see why we differ!) a rather higher value (and been v.wrong!) So
Are you aware that - for a Dc current Ic=1mA - the term you propose to neglect would be app. 50% of the effective feedback resistor?
* absolutely yes! At least, I am now you've reminded me.
Since the figure I would have guessed for re would have been that size, I can't see why it didn't strike me as worth worrying about at the time. I can only say that I was trying to get a rough idea of what was going on, and when the result came out near enough (for my poor standards) to what was wanted, I didn't bother to think about any more careful work.

*(Though, just as I might have done, you've taken a different value of standing current (1 mA instead of the 5.5 mA used in the cct) just to emphasise your point! And there would be an interesting conversation to have about the variation of gain with emitter current and how it affects the stage gain, if only I dared enter into such a discussion.)

So I apologise if I offended you.
My comment was just a light-hearted, flippant allusion to our past disagreement (on models vs reality), which has always detered me from joining any further discussions where you are posting.
I only risked it this time, because I thought your point 1 was relevant and well made. I should have stuck at that and maybe just given your post a like.

#### LvW

Indeed, you have clarified a misunderstanding ....and thats, finally, a good news.
Thank you
LvW

"Amplifier circuit"

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